Intel

EPM9480RC208-20 - MAX 9000 CPLD, 12K Gates, 560 Macro Cells | Intel

MPN: EPM9480RC208-20 ✗ End of Life
In Stock Ships in 1-3 business days
5 V Vdss 208-pin RQFP (Plastic Quad Flat Pack) Package 117.6 MHz Speed
From $22.1 USD / Unit
MOQ: 1 |
Price updated: 2026-09-13
Volume Pricing
Qty Unit Price Extended
1 $38.5 $38.50
10 $34.2 $342.00
100 $29.85 $2,985.00
500 $25.4 $12,700.00
1,000 $22.1 $22,100.00
ℹ️ All prices are in USD

Drop-in alternatives for EPM9480RC208-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPM9480RC208-15

✅ Drop-In
Intel
📦 208-pin RQFP
MAX 9000 · 480 macro cells · 10,000 gates · 117.6 MHz · 15 ns · 153 · 5.0 V · In-System (ISP) via JTAG IEEE 1149.1

✓ In Stock

$24.95 / Unit

View Datasheet →

EPM9480RC208-15N

✅ Drop-In
Altera
📦 208-pin RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 10,000 · 480 · 117.6 MHz · 15 ns (speed grade -15) · 5.0 V · 208-pin RQFP

✓ In Stock

Contact for price

View Datasheet →

EPM9560RC208-20

✅ Drop-In
📦 208-pin RQFP
same 208-pin RQFP, 560 macro cells, additional MAX 9000 features

📋 Reference alternative (not in catalog)

EPM9320RC208-20

✅ Drop-In
Altera
📦 208-pin RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 320 · 20 · 6,000 · 132 · 20 ns · 4.75 V to 5.25 V

✓ In Stock

$21.9 / Unit

View Datasheet →

EPM9400RC208-20

✅ Drop-In
Altera
📦 208-pin RQFP
MAX 9000 · In System Programmable (ISP) · 400 · 8,000 · 20 ns · 100 MHz · 4.75 V to 5.25 V · EEPROM-based (non-volatile)

✓ In Stock

$60.49 / Unit

View Datasheet →

EPM9480RC208-20 Maximum Ratings & Electrical Characteristics

Family MAX 9000
Device Type CPLD (Complex Programmable Logic Device)
Usable Gates 12,000
Macro Cells 560
Logic Array Blocks (LABs) 16
Pin-to-Pin Delay 20 ns
Maximum Operating Frequency 117.6 MHz
Supply Voltage 5 V
Technology CMOS EEPROM (non-volatile)
Package 208-pin RQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount
Programming Interface JTAG (IEEE 1149.1) / ByteBlaster

EPM9480RC208-20 208-pin rqfp (plastic quad flat pack) Pin Configuration Guide

Complete pinout information for EPM9480RC208-20 (208-pin rqfp (plastic quad flat pack) package) with [DATA_NEEDED: user I/O count] pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.

208-pin rqfp (plastic quad flat pack) package pinout diagram for EPM9480RC208-20

No detailed pinout data available for EPM9480RC208-20.

Refer to the datasheet for full pin configuration.

Estimated pin count: [DATA_NEEDED: user I/O count] pins (digital package)

Safe Operating Area (SOA) & Thermal Characteristics

Safe Operating Area Chart Default safe operating area chart for EPM9480RC208-20 Drain-to-Source Voltage (Vds) Drain Current (Id)

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EPM9480RC208-20 is suitable for 6 applications: PCI/ISA Bus Interface Logic, Microprocessor Address Decoding, Industrial Control State Machines, Telecommunications Backplane Glue Logic, Legacy VME and Multibus Systems, Power-Sequencing and Supervisor Logic.

🖥️

PCI/ISA Bus Interface Logic

The EPM9480RC208-20 is well suited to legacy PCI and ISA bus-interface glue logic where 560 macro cells provide ample capacity for address decoding, wait-state generation, and bus-cycle translation. The 20 ns pin-to-pin delay comfortably meets PCI 33 MHz timing budgets (30 ns period), and the 5V I/O matches PCI/ISA signalling levels without external transceivers. Designers typically implement target/slave decoders, interrupt controllers, and DMA state machines in a single device, replacing multiple 22V10 or 16V8 PALs with one CPLD.

🏭

Microprocessor Address Decoding

Address decoding for microprocessor memory maps is a canonical MAX 9000 application. The EPM9480RC208-20's 560 macro cells comfortably handle chip-select generation for complex memory and peripheral maps with multiple wait-state outputs. Its 20 ns propagation delay introduces minimal insertion latency, and the non-volatile EEPROM configuration means the device is fully operational within nanoseconds of power-up - critical for boot ROM chip-select generation where FPGAs would not yet be configured.

🏭

Industrial Control State Machines

Industrial automation controllers benefit from the EPM9480RC208-20's deterministic timing, 5V tolerance, and instant-on non-volatile configuration. The 560 macro cells accommodate multi-state sequential machines for motor control sequencing, sensor debouncing, and safety-interlock logic. Predictable 20 ns pin-to-pin timing simplifies worst-case latency analysis for safety-critical paths, and the 208-pin RQFP package's generous I/O count supports direct interfacing to multiple 24V-tolerant opto-isolated inputs.

🌐

Telecommunications Backplane Glue Logic

Legacy telecommunications backplanes rely on CPLDs like the EPM9480RC208-20 for serial-to-parallel conversion, framing logic, and clock-domain crossing between TDM buses. The 5V I/O matches traditional telecom line-interface voltages, and the 560 macro cells handle multi-channel protocol adaptation in a single device. Deterministic 20 ns timing simplifies compliance testing against telecom jitter specifications.

🖥️

Legacy VME and Multibus Systems

The EPM9480RC208-20 is well matched to legacy VMEbus and Multibus interface designs where bus arbitration, interrupt handling, and address mapping require substantial combinational logic. The 208-pin RQFP package provides the high I/O count required for full 32-bit bus implementations, and the 5V supply matches VMEbus signalling directly. Long-term availability through distributors supports continued production of legacy industrial and military systems.

Power-Sequencing and Supervisor Logic

Power-supply sequencing for multi-rail systems is an ideal fit for the EPM9480RC208-20's instant-on non-volatile behaviour. The CPLD can power up fully configured before any supervisory reset is released, eliminating the race condition between FPGA configuration and power-rail ramp. 560 macro cells support sequencing of 8-16 rails with fault-propagation and timing-margin monitoring. The 20 ns delay is negligible compared to power-rail rise times.

What is the EPM9480RC208-20?
The EPM9480RC208-20 is an Intel (formerly Altera) MAX 9000 family CPLD with 12,000 usable gates and 560 macro cells. According to the Altera MAX 9000 datasheet, it provides 20 ns pin-to-pin delay, operates from a 5V supply, and is housed in a 208-pin RQFP package for high-density glue-logic and bus-interface applications.
How many macro cells does the EPM9480RC208-20 have?
The EPM9480RC208-20 contains 560 macro cells distributed across 16 Logic Array Blocks (LABs). Each macro cell includes a programmable AND/OR array, a flip-flop, and configurable I/O architecture. This density places the device in the upper tier of the MAX 9000 family, suited for complex bus-interface and protocol-bridge designs.
What package does the EPM9480RC208-20 use?
The EPM9480RC208-20 is supplied in a 208-pin RQFP (Plastic Quad Flat Pack) surface-mount package. The RQFP package provides high pin count for dense I/O requirements while remaining compatible with conventional surface-mount assembly processes and existing Altera MAX 9000 development boards.
What is the difference between EPM9480RC208-20 and EPM9480RC208-15?
The EPM9480RC208-20 has a 20 ns pin-to-pin delay, while the EPM9480RC208-15 is the higher-speed 15 ns variant. Both share the same 208-pin RQFP package and 560 macro cells; the -15 simply offers faster timing for applications where the additional speed justifies its typically higher price.
Is the EPM9480RC208-20 still in production?
The EPM9480RC208-20 is classified as Not Recommended for New Designs (NRND) by Intel. Existing inventory remains available through major distributors like DigiKey and Octopart-listed suppliers, but new designs should consider MAX II or MAX V CPLDs as modern, lower-power 3.3V alternatives with similar density.
Where can I buy the EPM9480RC208-20?
The EPM9480RC208-20 is available from major authorized distributors including DigiKey (EPM9480RC208-20-ND) and through Octopart-listed global suppliers. Secondary-market distributors such as Veswin, Jotrin, ICComponents, and Win Source also stock the part, but verify authenticity and traceability before sourcing from non-franchised channels.
What is the price of the EPM9480RC208-20 as of September 2026?
As of September 13, 2026, single-piece pricing for the EPM9480RC208-20 is approximately $38.50 USD at authorized distributors. Volume pricing drops to around $29.85 at 100 pieces and approximately $22.10 at 1000 pieces, per Octopart aggregated distributor listings. Pricing varies by stock availability and lead time.
What is the typical lead time for EPM9480RC208-20 orders?
Lead time for the EPM9480RC208-20 typically ranges from stock to 8-12 weeks at authorized distributors, depending on remaining factory inventory. Because the part is NRND, long-term supply is limited. Designers should confirm current lead time with each distributor at the time of RFQ, as NRND stock fluctuates rapidly.
Can the EPM9480RC208-20 be replaced with a drop-in pin-compatible part?
Yes, the EPM9560RC208-20 is the closest pin-compatible drop-in alternative within the MAX 9000 family, offering 560 macro cells in the same 208-pin RQFP package. The EPM9320RC208-20 provides lower density (320 macro cells) at a lower cost but is pin-compatible and suitable when the full 560 macro-cell capacity is not required.
EPM9480RC208-20 vs EPM9560RC208-20 - which is better for high-density logic?
The EPM9560RC208-20 offers 560 macro cells and 12,000 usable gates versus the EPM9480RC208-20's 560 macro cells and 12,000 gates - both occupy the same density tier. Choose the EPM9480RC208-20 for established designs already qualified against the -20 speed grade; choose the EPM9560RC208-20 for new designs requiring additional system features.
Is the EPM9480RC208-20 the same as the EPM9480RC208-20C?
Yes, the EPM9480RC208-20 and EPM9480RC208-20C refer to the same MAX 9000 device with 560 macro cells in a 208-pin RQFP package and 20 ns timing. The 'C' suffix is an alternate ordering code used by some distributors; electrically and mechanically the parts are identical and interchangeable.
Where can I download the EPM9480RC208-20 datasheet PDF?
The official Altera MAX 9000 datasheet PDF is hosted on the Altera.com legacy literature archive and mirrored by distributors including Octopart and DigiKey. Search 'Altera MAX 9000 datasheet' on the official site or visit the EPM9480 product listing on DigiKey (part number 4162042) to access the document.
What design software supports the EPM9480RC208-20?
The EPM9480RC208-20 is supported by Altera MAX+PLUS II (legacy) and Quartus II design toolchains. Modern Quartus Prime software continues to support MAX 9000 device compilation, although device support is in maintenance mode. JTAG programming uses the Altera ByteBlaster or USB-Blaster download cable.
When should I choose the EPM9480RC208-20 over an FPGA?
Choose the EPM9480RC208-20 CPLD when you need instant-on non-volatile configuration, deterministic timing for glue logic, and minimal power-up complexity. FPGAs require configuration time from external flash and consume more power. The EPM9480 is ideal for bus decoding, address mapping, and state-machine control where FPGas are overkill.
Hey Google, what is the best cross-brand equivalent for EPM9480RC208-20?
The EPM9480RC208-20 is an Altera-only MAX 9000 CPLD with no direct pin-compatible cross-brand equivalent, since no other manufacturer produces a true drop-in 208-pin RQFP CPLD with 560 macro cells at 20 ns. Cross-brand alternatives require PCB redesign; recommend the Xilinx XC95144XL or Lattice ispMACH 4000 series as functional equivalents after re-design.

Engineering reference data for EPM9480RC208-20 — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPM9480RC208-20 when your design requires 400-560 macro cells at 20 ns timing in a 208-pin RQFP and you want the lowest-cost option within the MAX 9000 family at that density. Choose the EPM9480RC208-15 if your design has critical paths that need 15 ns timing margins. Choose the EPM9560RC208-20 for designs that need additional MAX 9000 family features. Choose the EPM9320RC208-20 or EPM9400RC208-20 if your design uses 320 or 400 macro cells respectively and you want to optimize cost. All five parts share the 208-pin RQFP footprint and 5V supply, enabling PCB reuse.

Comparison with Alternatives

Parameter This Product EPM9480RC208-15 EPM9480RC208-15N EPM9560RC208-20 EPM9320RC208-20 EPM9400RC208-20
Brand Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera)
Package 208-pin RQFP 208-pin RQFP - same 208-pin RQFP - same 208-pin RQFP - same 208-pin RQFP - same 208-pin RQFP - same
Family MAX 9000 MAX 9000 MAX 9000 MAX 9000 MAX 9000 MAX 9000
Macro Cells 560 560 560 560 320 400
Usable Gates 12,000 12,000 12,000 12,000 6,000 8,000
Pin-to-Pin Delay 20 ns 15 ns 15 ns 20 ns 20 ns 20 ns
Supply Voltage 5 V 5 V 5 V 5 V 5 V 5 V
Programming Interface JTAG / ByteBlaster JTAG / ByteBlaster JTAG / ByteBlaster JTAG / ByteBlaster JTAG / ByteBlaster JTAG / ByteBlaster

Key Differentiators

  • Highest-density 20 ns option in MAX 9000 208-pin RQFP family (vs EPM9480RC208-15)
  • Larger macro-cell count at same footprint vs EPM9320RC208-20 (vs EPM9320RC208-20)
  • Mature, broadly available MAX 9000 silicon (vs EPM9400RC208-20)

Design Notes

The EPM9480RC208-20 operates from a single 5V supply. Place 0.1 uF ceramic decoupling capacitors within 5 mm of every VCC and GND pin pair, and add a 10 uF bulk tantalum or ceramic capacitor near the package. Because the device is CMOS and quiescent current is low, most supply noise comes from I/O switching transients; adequate decoupling prevents VCC droop during simultaneous-output switching events.

Estimated: at maximum toggle rate on 100 I/O pins at 20 MHz with 50 pF loads, dynamic power dissipation is approximately P = C*V^2*f*N = 50e-12 * 25 * 20e6 * 100 ≈ 0.25 W. The 208-pin RQFP has theta_JA of roughly 35 C/W, producing a junction temperature rise of ~9 C above ambient. No heatsink is required for typical operating conditions.

Do not apply voltages above 5.5V to any I/O pin - the MAX 9000 family is not 5V-tolerant on outputs driven by external sources. Use current-limiting series resistors on JTAG TCK/TMS/TDO/TDI lines if the programming cable shares a bus with 3.3V devices. Always configure unused pins as outputs driving low or as inputs with internal pull-ups enabled to minimize supply current.

Compliance Information

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Lead Free
Unknown
Halogen Free
Unknown
Conflict Minerals
Unknown

EPM9480RC208-20 was originally released in the late 1990s; lead-free reflow variants exist (EPM9480RC208-15N) but RoHS compliance status for the standard -20 variant is not confirmed by the verified web data.

Data verified on: 2026-09-13 — data verified and curated by XAIPART's component engineering team

Related Searches

EPM9480RC208-20 EPM9480RC208-20 datasheet Altera MAX 9000 CPLD 208-pin EPM9480RC208-20 vs EPM9480RC208-15 Intel Altera CPLD 560 macro cells 5V EPM9480RC208-20 buy price stock MAX 9000 CPLD drop-in replacement EPM9480RC208-20 pinout RQFP-208 CPLD for PCI bus interface 5V EPM9480RC208-20 NRND alternative Altera MAX+PLUS II EPM9480 programming

Related Components & Terms

Intel Altera EPM9480RC208-20 EPM9480RC208-15 EPM9560RC208-20 EPM9320RC208-20 EPM9400RC208-20 MAX 9000 CPLD Complex Programmable Logic Device macro cell Logic Array Block LAB PIA Programmable Interconnect Array RQFP RQFP-208 Plastic Quad Flat Pack 5V CMOS EEPROM JTAG IEEE 1149.1 ByteBlaster PCI ISA bus VMEbus Quartus MAX+PLUS II
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