Altera

EPM9560RC208-20C - MAX 9000 CPLD 560 Macro Cells | Altera

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5.0 V Vdss 208-pin RQFP (Power Quad Flat Pack) Package 100 MHz Speed EEPROM (non-volatile) Memory

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MOQ: 1 |

Preço atualizado: 2026-09-13

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Qtd.	Preço unitário	Total
1	$0	$0,00
10	$0	$0,00
100	$0	$0,00
500	$0	$0,00
1.000	$0	$0,00

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EPM9560RC208-20C Visão geral

The Altera EPM9560RC208-20C is a MAX 9000 family EEPROM-based complex programmable logic device (CPLD) with 560 macrocells, 12,000 usable gates, 772 flip-flops, and 149 user I/O pins, delivering a 20 ns pin-to-pin propagation delay in a 208-pin RQFP (Power Quad Flat Pack) package operating from a 5.0 V supply.

A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and macrocells with a non-volatile EEPROM configuration memory, allowing the device to retain its logic configuration without an external configuration PROM. Within the programmable logic hierarchy, the CPLD sits between simple PLDs (PAL/GAL) and FPGAs: CPLDs offer deterministic, pin-to-pin timing and instant-on operation, while FPGAs provide higher logic density at the cost of external configuration memory. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture and supports 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface.

Key differentiators of the EPM9560RC208-20C include its 560 macrocells (the highest density in the MAX 9000 family), 149 configurable I/O lines, 12,000 usable gates, and 20 ns commercial-grade propagation delay. The EEPROM configuration cell provides non-volatile, instant-on operation, eliminating the configuration PROM required by SRAM-based FPGAs and improving system security against configuration readback.

The device uses CMOS EEPROM technology with 5.0 V core and I/O operation, and is offered in a 208-pin RQFP package (JESD-30 code S-PQFP-G208) with gull-wing terminals. The MAX 9000 architecture routes signals through a programmable interconnect array (PIA) that provides predictable, fixed delays between logic array blocks, enabling worst-case timing analysis without post-fit simulation.

Typical applications include glue logic consolidation in industrial control boards, bus interface and address decoding in legacy 5 V microprocessor systems, state machines for instrumentation, and prototyping of moderate-complexity digital logic where instant-on operation and 5 V compatibility are required.

When designing with the EPM9560RC208-20C, note that the device is a legacy 5 V CPLD; verify availability of the MAX+PLUS II development toolchain and confirm the target board provides a clean 5.0 V rail with adequate decoupling on every VCC pin. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.

Alternativas drop-in para EPM9560RC208-20C — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM9560RC208-20C (mesmo formato e footprint) — diferindo em Package, Propagation Delay (tPD), In-System Programmability, Speed Grade, RoHS Status.

EPM9400RC208-20

Altera

Package: 208-pin RQFP (28x28 mm)

Speed Grade: -20 (20 ns)