Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

N.º da peça: EPM9560RC210-20 ⚠ Última compra

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5 V Vdss RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) Package 12 ns Speed

A partir de $60 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-13

Preços por volume

Qtd.	Preço unitário	Total
1	$75	$75,00
10	$70	$700,00
100	$65	$6.500,00
500	$62.5	$31.250,00
1.000	$60	$60.000,00

ℹ️ Todos os preços estão em USD

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EPM9560RC210-20 Visão geral

The Altera EPM9560RC210-20 is a high-density member of the MAX 9000 family of Complex Programmable Logic Devices (CPLDs), delivering approximately 560 macrocells (12,000 usable gates) in a 210-pin Power Quad Flat Pack (RQFP) package with -20 speed grade. The MAX 9000 family is Altera's first-generation high-density CPLD family built on a 0.65um EEPROM process, combining the non-volatility of EPROM with in-system programmability via the Altera MAX+PLUS II development environment. The -20 suffix denotes a 20ns pin-to-pin propagation delay (tPD) for combinational logic at room temperature, making it suitable for glue-logic and high-volume state-machine replacement in cost-sensitive industrial designs.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL spld devices and high-density FPGAs in the programmable logic hierarchy: PAL/GAL < CPLD < FPGA. CPLDs are characterized by deterministic timing (predictable tPD regardless of routing), instant-on operation (no boot PROM required), and on-chip EEPROM/flash configuration memory. Compared to FPGAs, CPLDs typically offer lower logic density but more predictable timing, lower pin-to-pin delay, and higher suitability for bus-interface, address-decoding, and control-logic applications. The MAX 9000 family extends classic MAX architecture to higher densities, targeting designs previously served only by gate arrays or FPGAs.

Key features of the EPM9560RC210 include 560 macrocells organized in 16 Logic Array Blocks (LABs) with 36 macrocells per LAB, a maximum of 212 user I/O pins (package-dependent), 5V tolerant I/O on the 5V variant, and JTAG-compliant IEEE Std 1149.1 boundary-scan support for board-level testability. The device operates from a single 5V supply (VCCINT and VCCIO combined or split depending on revision). Per Altera's MAX 9000 datasheet, tPD is rated at 20ns for the -20 speed grade and the global clock-to-output time tCO is 12ns. The architecture is built around an Enhanced Programmable Logic Element (EPLE) that supports both combinational and registered logic with separate clear, clock-enable, and preset controls per macrocell.

Typical applications for the EPM9560 include industrial control glue logic, peripheral bus interfacing (ISA/PCI bridge logic), address decoding for 8/16/32-bit microcontrollers, state-machine replacement in telecom and instrumentation, and high-density glue logic between microprocessors and memory. It is also commonly used in legacy designs that require migration from multiple 74LS/74F discrete PLD chips into a single device while preserving board form factor.

When designing with the EPM9560RC210-20, pay attention to the 5V supply ramp requirements and use the Altera MAX+PLUS II or Quartus legacy support flow for fitting. The 210-pin RQFP package requires careful PCB layout - use a 0.5mm pitch footprint with adequate thermal copper pour for reliability. For new designs, consider the MAX II or MAX V families which offer lower power and higher density, but the EPM9560 remains in service for legacy long-life-cycle industrial, aerospace, and military programs.

Alternativas drop-in para EPM9560RC210-20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM9560RC210-20 (mesmo formato e footprint) — diferindo em Package, In-System Programmability, Device Type, RoHS Status, User I/O Pins.

EPM9560RC208-15

Altera

Package: 208-pin RQFP (Power Quad Flat Pack)

In-System Programmability: Yes, via IEEE Std. 1149.1 JTAG

Device Type: EEPROM-based Complex Programmable Logic Device (CPLD)