LTC2156IUP-14 - Dual 14-Bit 210Msps ADC 64-QFN | Analog Devices
N.º da peça: LTC2156IUP-14 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $178.37 | $178,37 |
| 10 | $165.5 | $1.655,00 |
| 100 | $152.2 | $15.220,00 |
| 500 | $142.4 | $71.200,00 |
| 1.000 | $134.1 | $134.100,00 |
LTC2156IUP-14 Visão geral
A pipelined ADC is a multi-stage converter architecture that digitizes an analog input through a cascade of low-resolution flash sub-converter stages combined with inter-stage residue amplification and digital error correction. Pipelined ADCs occupy the middle ground between low-power successive-approximation (SAR) converters and very-high-speed flash ADCs, delivering hundreds of megasamples per second at moderate resolution. In a system hierarchy, the LTC2156IUP-14 belongs to the broader category of data converters -> analog-to-digital converters (ADCs) -> high-speed ADCs -> pipelined ADCs, which is one of the principal building blocks of modern signal acquisition and digital signal processing (DSP) systems.
Key features include dual simultaneous-sampling channels, an easy-to-drive 1.5 V peak-to-peak differential input range, 1.25 GHz full-power sample-and-hold bandwidth, an optional on-chip clock duty-cycle stabilizer, and low-power Sleep and Nap modes for power-constrained systems. The serial SPI port enables register-level configuration of output formats, gain, and calibration, while DDR LVDS outputs ease the board-level routing of high-speed digital data into an FPGA or ASIC.
Typical applications include communications basestations, radar digitizers, medical imaging front-ends, and high-end test and measurement instrumentation. The wide SFDR and fast sampling rate allow direct digitization of IF signals in software-defined radio (SDR), while the dual channels support MIMO or I/Q signal chains. A 1.5 Vp-p input range simplifies the front-end driver design relative to competitors that require 2 Vp-p swings.
When designing with this device, place bypass capacitors as close as possible to the supply pins and route the differential analog inputs as a tightly-coupled pair to preserve common-mode rejection at the rated SFDR. The clock trace must be short and well-terminated to meet the 210 Msps conversion rate without violating setup-and-hold timing into the receiver.
Alternativas drop-in para LTC2156IUP-14 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2156IUP-14 (mesmo formato e footprint) — diferindo em Package, Operating Temperature Range, SNR, Resolution, Sampling Rate.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2157IUP-14
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2155IUP-14
✅ Drop-In✓ Em estoque
$107.04 / unidade
Ver ficha técnica →LTC2156CUP-14
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2157CUP-14
✅ Drop-In✓ Em estoque
$132.4 / unidade
Ver ficha técnica →LTC2155CUP-14
✅ Drop-In✓ Em estoque
$78.95 / unidade
Ver ficha técnica →ADS62P49IRGCT
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2156IUP-14 Classificações máximas e características elétricas
| Manufacturer | Analog Devices |
| Part Number | LTC2156IUP-14 |
| Converter Type | Dual ADC, Pipelined |
| Resolução | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Taxa de amostragem | 210 Msps |
| Input Type | Differential |
| Faixa de tensão de entrada | 1.5 Vp-p |
| Tensão de alimentação | 1.8 V single supply |
| Power Consumption | 650 mW |
| SNR | 70 dB |
| SFDR | 90 dB |
| Output Interface | DDR LVDS |
| Configuration Interface | Serial SPI |
| Full-Power Bandwidth | 1.25 GHz |
| Encapsulamento | 64-QFN (9x9 mm) |
| Faixa de temperatura de operação | -40 C to +85 C (IUP grade) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant (PBF suffix) |
| Lead-Free | Yes (PBF suffix) |
Configuração de pinos do LTC2156IUP-14
| Pino 1 | GND — Ground |
| Pino 2 | AIN1+ — Channel 1 differential analog input, positive |
| Pino 3 | AIN1- — Channel 1 differential analog input, negative |
| Pino 4 | GND — Ground |
| Pino 5 | VCM — Common-mode voltage output for input driver biasing |
| Pino 6 | GND — Ground |
| Pino 7 | AIN2+ — Channel 2 differential analog input, positive |
| Pino 8 | AIN2- — Channel 2 differential analog input, negative |
| Pino 9 | GND — Ground |
| Pino 10 | SENSE — Reference/sense pin for supply regulation |
| Pino 11 | VDD — 1.8 V analog supply |
| Pino 12 | GND — Ground |
| Pino 13 | CLK+ — Differential clock input, positive |
| Pino 14 | CLK- — Differential clock input, negative |
| Pino 15 | GND — Ground |
| Pino 16 | OGND — Output driver ground (LVDS) |
| Pino 17 | OVDD — LVDS output driver supply |
| Pino 18 | OUT1A+/OUT1A- — Channel 1 LVDS DDR data output pair A |
| Pino 19 | OUT1B+/OUT1B- — Channel 1 LVDS DDR data output pair B |
| Pino 20 | OUT1CLK+/OUT1CLK- — Channel 1 LVDS DDR clock output pair |
| Pino 21 | OGND — Output driver ground |
| Pino 22 | OVDD — LVDS output driver supply |
| Pino 23 | OUT2A+/OUT2A- — Channel 2 LVDS DDR data output pair A |
| Pino 24 | OUT2B+/OUT2B- — Channel 2 LVDS DDR data output pair B |
| Pino 25 | OUT2CLK+/OUT2CLK- — Channel 2 LVDS DDR clock output pair |
| Pino 26 | OGND — Output driver ground |
| Pino 27 | OVDD — LVDS output driver supply |
| Pino 28 | CS — SPI chip select (active low) |
| Pino 29 | SCK — SPI serial clock |
| Pino 30 | SDI — SPI serial data input |
| Pino 31 | SDO — SPI serial data output (open-drain, requires external pull-up) |
| Pino 32 | GND — Ground |
| Pino 33 | RESET — Reset input (active low) |
| Pino 34 | PDWN — Power-down control input |
| Pino 35 | NAP — Nap mode control input |
| Pino 36 | SLEEP — Sleep mode control input |
| Pino 37 | GND — Ground |
| Pino 38 | VDD — 1.8 V analog supply |
| Pino 39 | VDD — 1.8 V analog supply |
| Pino 40 | GND — Ground |
| Pino 41 | OGND — Output driver ground |
| Pino 42 | OVDD — LVDS output driver supply |
| Pino 43 | GND — Ground |
| Pino 44 | VDD — 1.8 V analog supply |
| Pino 45 | MODE — Operating mode select |
| Pino 46 | GND — Ground |
| Pino 47 | AIN1P — Channel 1 auxiliary analog input positive (internal PGA) |
| Pino 48 | AIN1N — Channel 1 auxiliary analog input negative (internal PGA) |
| Pino 49 | GND — Ground |
| Pino 50 | AIN2P — Channel 2 auxiliary analog input positive (internal PGA) |
| Pino 51 | AIN2N — Channel 2 auxiliary analog input negative (internal PGA) |
| Pino 52 | GND — Ground |
| Pino 53 | VDD — 1.8 V analog supply |
| Pino 54 | GND — Ground |
| Pino 55 | VREF — Internal/decoupling reference voltage pin |
| Pino 56 | GND — Ground |
| Pino 57 | VDD — 1.8 V analog supply |
| Pino 58 | OGND — Output driver ground |
| Pino 59 | OVDD — LVDS output driver supply |
| Pino 60 | DCO+/DCO- — Duty cycle stabilizer / DDR clock output pair |
| Pino 61 | FRAME+/FRAME- — Frame clock LVDS output pair |
| Pino 62 | OGND — Output driver ground |
| Pino 63 | OVDD — LVDS output driver supply |
| Pino 64 | NC — Not connected (per datasheet) |
Aplicações típicas
LTC2156IUP-14 é adequado para 6 aplicaçãos: Communications Basestation Receiver, Software-Defined Radio (SDR) IF Digitizer, Radar Signal Digitization, Medical Imaging Front End, Test and Measurement Instrumentation, Industrial Data Acquisition Systems.
Communications Basestation Receiver
The LTC2156IUP-14's dual 14-bit 210 Msps channels and 70 dB SNR make it well suited for digitizing wideband IF signals in 4G/5G basestation receivers. Both channels sample simultaneously, which is critical for diversity or MIMO antenna paths where matched channel gain and phase must be preserved across the analog front end. With 90 dB SFDR, the ADC can resolve small wanted signals next to large blockers without raising the noise floor or generating intermodulation spurs. The 1.5 Vp-p differential input range simplifies the front-end driver design relative to parts that require 2 Vp-p swings, and the DDR LVDS output bus interfaces cleanly with modern FPGAs used for digital down-conversion. Power consumption of 650 mW from a single 1.8 V supply keeps thermal loading manageable in outdoor basestation equipment.
Recomendado
Software-Defined Radio (SDR) IF Digitizer
In software-defined radio platforms, the LTC2156IUP-14 can directly digitize IF signals up to about 300 MHz bandwidth, allowing the digital backend (FPGA + DSP) to perform channelization, demodulation, and filtering in software. The 1.25 GHz full-power sample-and-hold bandwidth and 210 Msps conversion rate comfortably cover typical L-band and S-band IF frequencies used in modern wireless and military radio designs. The SPI configuration port allows the host processor to fine-tune gain, offset, and output format at runtime. The DDR LVDS output bus maintains signal integrity at the rated sample rate while minimizing EMI on the crowded SDR PCB, and the 1.8 V single supply simplifies the radio's power tree. Nap and Sleep modes are useful for time-division duplex (TDD) systems that must reduce power when not transmitting.
Recomendado
Radar Signal Digitization
The LTC2156IUP-14's wide SFDR (90 dB) and dual simultaneous-sampling channels are well matched to pulsed-Doppler and FMCW radar front ends, where preserving dynamic range next to clutter and large nearby targets is critical. Its 210 Msps sample rate supports IF bandwidths up to about 100 MHz, which is sufficient for many short-range automotive and perimeter-surveillance radar systems. The pipelined architecture provides deterministic latency, which simplifies range-bin processing in the digital backend. Nap and Sleep modes allow the radar to duty-cycle its power budget between transmit bursts, reducing average dissipation in battery-powered deployments. The 64-QFN exposed pad provides good thermal coupling for sustained high-duty-cycle operation, and the industrial -40 C to +85 C grade supports outdoor radar installations.
Recomendado
Medical Imaging Front End
The LTC2156IUP-14 supports medical imaging systems including ultrasound beamformers, where the dual simultaneous-sampling channels allow direct digitization of I/Q or paired transducer channels with matched gain and phase. The 14-bit resolution and 70 dB SNR provide the dynamic range required to resolve small echo amplitudes next to strong specular reflectors, while the 210 Msps rate supports high-frequency ultrasound transducers operating in the 5-15 MHz range. The DDR LVDS output bus reduces digital noise coupling into the sensitive analog front end, which is critical when amplifying microvolt-level echo signals. The 1.8 V supply simplifies medical device safety and isolation design compared to higher-voltage ADC rails. The -40 C to +85 C industrial temperature grade supports portable imaging carts and field-deployable diagnostic equipment.
Recomendado
Test and Measurement Instrumentation
The LTC2156IUP-14 fits high-end oscilloscope, spectrum analyzer, and arbitrary waveform digitizer front ends where 14-bit vertical resolution and 210 Msps real-time sampling rate deliver sub-percent amplitude accuracy on repetitive waveforms. Dual simultaneous-sampling channels simplify two-channel oscilloscope designs without requiring two separate ADC boards. The 90 dB SFDR ensures that harmonic measurements of high-purity signals remain undistorted, while the 1.5 Vp-p input range matches typical active probe output levels. The SPI configuration port allows the instrument's host controller to apply per-channel calibration coefficients at runtime. DDR LVDS outputs feed modern FPGA-based acquisition engines, and the industrial temperature grade supports lab and field environments equally.
Recomendado
Industrial Data Acquisition Systems
The LTC2156IUP-14 serves high-channel-count industrial data acquisition platforms such as multi-axis vibration monitoring systems, acoustic emission analyzers, and high-speed control-loop digitizers. Each dual-channel ADC digitizes two sensors simultaneously, which is essential for phase-locked vibration analysis and differential pressure measurements. The 1.5 Vp-p differential input range pairs cleanly with piezoelectric and bridge-sensor signal chains. The 1.8 V single supply reduces overall board power and simplifies multi-board chassis designs. The -40 C to +85 C industrial temperature range supports factory floor, outdoor, and ruggedized deployments without additional thermal management. SPI configuration allows the system controller to tune offset and gain per channel at calibration time, compensating for sensor-to-sensor variation.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2156IUP-14 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2157IUP-14 | LTC2155IUP-14 | LTC2156CUP-14 | LTC2157CUP-14 | LTC2155CUP-14 | ADS62P49IRGCT |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Texas Instruments |
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same footprint, verify pinout |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sampling Rate | 210 Msps | 250 Msps (+19%) | 170 Msps (-19%) | 210 Msps (same) | 250 Msps (+19%) | 170 Msps (-19%) | 250 Msps (+19%) |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 3.3 V |
| Output Interface | DDR LVDS | DDR LVDS | DDR LVDS | DDR LVDS | DDR LVDS | DDR LVDS | Parallel CMOS/LVDS |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) |
Principais diferenciais
- Dual simultaneous sampling at full 210 Msps per channel (vs LTC2155IUP-14 (170 Msps))
- Industrial -40 C to +85 C temperature grade (vs LTC2156CUP-14 (commercial 0-70 C))
- Pin-compatible upgrade path to 250 Msps (vs ADS62P49IRGCT (cross-brand 250 Msps))
Notas de projeto
Route the differential analog inputs (AIN+/AIN-) as a tightly-coupled 100 ohm differential pair, with ground reference on both sides. Keep the input traces as short as possible and place the differential driver amplifier within 1 cm of the ADC inputs to preserve 90 dB SFDR performance. Add 100 ohm differential termination at the ADC input pins to suppress reflections from the 1.25 GHz full-power bandwidth edges.
The exposed thermal pad on the bottom of the 64-QFN package must be soldered to a continuous ground plane with multiple thermal vias for heat dissipation. At 650 mW total power, this is critical for keeping junction temperature within ratings. Separate analog VDD and digital OVDD grounds should join only at the ADC exposed pad to prevent digital switching currents from coupling into the analog front end.
Use a low-jitter clock source such as the AD9516 or AD9517 to drive the CLK+/CLK- inputs. Total clock jitter should be below 200 fs RMS to maintain SNR at 210 Msps; higher jitter directly degrades SNR per the SNR = 6.02*N + 1.76 + 10*log(Fs/2) - jitter penalty formula. The clock duty-cycle stabilizer should be enabled when the source clock duty cycle deviates from 50% by more than 2%.
Estimated: bypass each VDD pin with a 1 uF ceramic + 0.1 uF ceramic + 10 uF bulk capacitor combination, placed within 5 mm of each pin. The OVDD pins powering the LVDS output drivers should be bypassed similarly but isolated by a ferrite bead from VDD to prevent output switching noise from corrupting the analog supply. Power-on sequence should bring up VDD first, then OVDD, to avoid latch-up at startup.
Do not apply analog input signals before VDD has reached its regulated 1.8 V level - the ESD diodes will forward-bias and can permanently damage the device. The SDO pin is open-drain with 200 ohm internal pull-down and requires an external 2 kohm pull-up resistor to VDD for readback to function. Sleep/Nap mode exit requires at least 100 clock cycles for the internal bias network to settle before accurate conversions resume.
Informações de conformidade
RoHS compliant per DigiKey listing for the #PBF suffix variant. Industrial temperature grade (-40 C to +85 C) - AEC-Q100 automotive qualification not pursued for this part number; consult factory for automotive-grade equivalents.
