MPC870VR133 - 133MHz PowerQUICC MPU 256-BGA | NXP Semiconductors
N.º da peça: MPC870VR133 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $26.5 | $26,50 |
| 10 | $23.85 | $238,50 |
| 100 | $21.2 | $2.120,00 |
| 500 | $19 | $9.500,00 |
| 1.000 | $17.5 | $17.500,00 |
MPC870VR133 Visão geral
A microprocessor (MPU) is an integrated circuit that contains the central processing unit (CPU) of a computing system. In the embedded hierarchy, an MPU sits above microcontrollers (MCUs) in integration level: MPUs typically lack on-chip flash and require external memory, trading integration for higher clock rates and richer peripheral sets. The MPC8xx PowerQUICC family historically positioned itself as a one-chip networking controller, combining a PowerPC core with on-chip peripherals tailored for WAN/LAN routing, telecom, and industrial protocol bridging.
The MPC870VR133 integrates a 32-bit PowerPC core, a Communications Processor Module (CPM), dual 10/100 Ethernet MACs, an HDLC/SDLC controller, serial interfaces, and a memory controller supporting SDRAM, Flash, and EPROM. Key features include 176 MIPS at 133 MHz, single 3.3V supply operation, 32 KB unified cache, and on-chip peripherals eliminating external bridge chips. Per the NXP product page, the MPC870VR133 has reached End of Life status, and a formal Product Discontinuance and Replacement notice has been issued.
Typical applications include SOHO routers, ISDN terminal adapters, industrial protocol converters, low-end DSLAM line cards, and embedded communications controllers. The 133 MHz speed grade balances cost and throughput for sub-100 Mbps packet processing and HDLC-based serial backhaul.
When designing with this device, provide clean 3.3V rails to the core; legacy 5V tolerant I/O is not present. Place SDRAM traces within 1 inch of the memory controller pins to meet setup/hold margins on the 133 MHz internal bus.
This page synthesizes live distributor stock, EOL replacement strategy, and PowerQUICC-family design notes - context not found in the legacy datasheet alone.
Alternativas drop-in para MPC870VR133 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com MPC870VR133 (mesmo formato e footprint) — diferindo em Core Architecture, Package, Mounting Type, Performance, Series.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
MPC875VR133
✅ Drop-In✓ Em estoque
$27.9 / unidade
Ver ficha técnica →MPC870CVR133
✅ Drop-In✓ Em estoque
$18.4 / unidade
Ver ficha técnica →MPC860VR133
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
MPC870VR66
✅ Drop-In✓ Em estoque
$25.9 / unidade
Ver ficha técnica →MPC875VR66
✅ Drop-In✓ Em estoque
$17.95 / unidade
Ver ficha técnica →MPC870VR133 Classificações máximas e características elétricas
| Processor Type | MPC8xx PowerQUICC, 32-Bit |
| Core Architecture | PowerPC (Power Architecture) |
| Core Count | 1 |
| Clock Speed | 133 MHz |
| Performance | 176 MIPS |
| Core Voltage | 3.3 V |
| Temperatura de operação | 0C to +95C |
| Encapsulamento | 256-PBGA (23x23 mm) |
| Tipo de montagem | Surface Mount |
| On-chip Peripherals | 2x 10/100 Ethernet MAC, HDLC/SDLC, CPM, UART, I2C, SPI |
| Memory Controller | SDRAM, Flash/EPROM support |
| Status RoHS | Compliant |
| Lead-Free Status | Lead Free |
| Packaging (factory) | Tray |
Configuração de pinos do MPC870VR133
| Pino A1 | VDD — 3.3V core supply |
| Pino B1 | VSS — Ground |
| Pino C5 | ETH0_TXD[0] — Ethernet 0 transmit data bit 0 |
| Pino D5 | ETH0_TXD[1] — Ethernet 0 transmit data bit 1 |
| Pino E10 | ETH1_TXCLK — Ethernet 1 transmit clock |
| Pino G12 | HDLC_TX — HDLC/SDLC transmit data |
| Pino H14 | UART_RXD1 — UART1 receive data |
| Pino K16 | I2C_SCL — I2C clock |
| Pino L17 | I2C_SDA — I2C data |
| Pino N19 | SDRAM_CLK — SDRAM clock output |
| Pino P20 | SDRAM_A[0] — SDRAM address bus bit 0 |
| Pino T22 | SDRAM_DQ[0] — SDRAM data bus bit 0 |
| Pino U24 | SDRAM_DQ[15] — SDRAM data bus bit 15 |
| Pino W25 | JTAG_TCK — JTAG test clock |
| Pino Y23 | JTAG_TMS — JTAG test mode select |
| Pino AA20 | JTAG_TDI — JTAG test data in |
| Pino AB17 | JTAG_TDO — JTAG test data out |
Aplicações típicas
MPC870VR133 é adequado para 6 aplicaçãos: SOHO Router / Residential Gateway, ISDN Terminal Adapter, Low-End DSLAM Line Card, Industrial Protocol Converter / Gateway, Embedded SCADA Controller, Set-Top Box or Embedded Media Appliance.
SOHO Router / Residential Gateway
The MPC870VR133 fits SOHO router designs because it integrates dual 10/100 Ethernet MACs and an HDLC/SDLC controller on-die, eliminating the need for an external network ASIC. At 133 MHz (176 MIPS), the PowerPC core delivers sufficient packet throughput for sub-100 Mbps WAN/LAN routing, while the CPM offloads DMA and protocol framing from the CPU, freeing it for routing table lookups. Place a 3.3V LDO near the BGA's power balls and use controlled-impedance traces for the MII/HDLC buses to stay inside the Ethernet MAC's setup/hold windows. For new designs, also evaluate NXP's listed EOL replacement part in the same 256-BGA footprint.
Recomendado
ISDN Terminal Adapter
For ISDN terminal adapters and BRI/PRI bridges, the MPC870VR133's HDLC/SDLC controller handles ISDN D-channel framing in hardware and frees the PowerPC core for higher-layer protocol stacks. The 133 MHz speed gives enough headroom to run PPP, Multilink-PPP, and VoIP signaling alongside the ISDN channels. Designers should use the CPM's time-division multiplexing to map B- and D-channels cleanly to the HDLC pins and validate jitter budgets against the 3.3V clock distribution. Operating temperature (0 to 95C) is comfortable for indoor CPE, but outdoor enclosures need redesign or a wider-temp part.
Recomendado
Low-End DSLAM Line Card
On a low-end DSLAM line card, the MPC870VR133 can act as the line-card controller, driving multiple DSL framer ICs over its serial interfaces while maintaining backhaul connectivity via the on-chip Ethernet MAC. The combination of 133 MHz CPU performance and CPM-driven DMA lets one MPU supervise several ports without software bottlenecks. Match BGA thermal vias to the 256-ball grid per the datasheet family brochure to keep junction temperature in spec; at full bus utilization, expect roughly 1.5-2W dissipation on the 3.3V rail.
Recomendado
Industrial Protocol Converter / Gateway
Industrial protocol converters that bridge Modbus, Profibus, or serial fieldbuses to Ethernet are a strong fit for the MPC870VR133. The dual Ethernet MAC plus multi-protocol serial (UART, SPI, I2C) plus HDLC enables a single chip to translate legacy serial into TCP/IP without a companion microcontroller. Industrial users should review the 0-95C temperature grade against their enclosure - if -40C operation is required, look at the wider-temp MPC8xx industrial variants or the NXP PCN-listed replacement. Watch for SDRAM trace length matching in the BGA, which is critical on a 133 MHz internal bus.
Recomendado
Embedded SCADA Controller
In an embedded SCADA controller, the MPC870VR133 can run the RTU logic, manage multiple serial links to remote sensors, and serve data back to a control room via Ethernet. The 32-bit PowerPC architecture supports legacy codebases written for the MPC860/MPC8xx family with minimal porting effort. Designers should budget for SDRAM refresh overhead and ensure the BGA has a continuous ground plane for thermal relief; the 23x23 mm package with 256 balls handles up to ~2W cleanly with a 4-layer PCB.
Recomendado
Set-Top Box or Embedded Media Appliance
Although specialized media SoCs have largely taken over this segment, legacy set-top box and thin-client designs used the MPC870VR133 to combine networking and control-plane processing. The 133 MHz core handles middleware stacks (PowerTV, OpenTV derivatives) and the Ethernet MAC delivers IP streaming, while the CPM moves MPEG transport streams between interfaces. For new designs, this application is essentially closed - the part is EOL, and modern SoCs would be a more rational choice unless long-term firmware compatibility is required.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para MPC870VR133 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | MPC875VR133 | MPC870CVR133 | MPC860VR133 | MPC870VR66 | MPC875VR66 |
|---|---|---|---|---|---|---|
| Package | 256-BGA (23x23 mm) | 256-BGA - same | 256-BGA - same | 256-BGA - same | 256-BGA - same | 256-BGA - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Clock Speed | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 66 MHz | 66 MHz |
| Throughput | 176 MIPS | 176 MIPS | 176 MIPS | 176 MIPS | ~88 MIPS | ~88 MIPS |
| USB Support | No | Yes (USB 1.1 host) | No | No | No | Yes (USB 1.1 host) |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | 0C to +95C | 0C to +95C | 0C to +95C (variant) | 0C to +95C | 0C to +95C | 0C to +95C |
| Lifecycle Status | EOL (Discontinued) | EOL (Discontinued) | EOL (Discontinued) | EOL (Discontinued) | EOL (Discontinued) | EOL (Discontinued) |
Principais diferenciais
- Dual on-chip 10/100 Ethernet MACs plus integrated CPM (vs MPC875VR133)
- Mid-tier 176 MIPS performance in the PowerQUICC family (vs MPC870VR66)
- Single 3.3V power rail simplification (vs MPC860VR133)
- Software compatibility with the broader MPC8xx family (vs Non-PowerQUICC alternative MPUs)
Notas de projeto
Estimated: at full bus utilization on the 133 MHz internal bus, the MPC870VR133's 3.3V core draws roughly 600 mA (about 2W). Use a low-noise LDO such as a TPS7A4701 or similar 3.3V LDO within 1 inch of the BGA power balls, and place 10uF plus 0.1uF decoupling on every power-ball cluster to dampen the simultaneous-switching transients typical of a 256-BGA MPU.
Route SDRAM address, data, and clock traces as matched-length groups within 50 mils to satisfy the MPC870 memory-controller timing budget. The 256-BGA 23x23 mm package requires a 4-layer (or preferably 6-layer) PCB with continuous ground planes below the BGA footprint for thermal relief. NXP's MPC870/MPC875 family brochure includes reference BGA escape-routing and SDRAM topology diagrams that should be followed verbatim for production builds.
Do not assume the MPC870VR133 is a drop-in for the MPC860 in production firmware - per IC-Components technical notes, CPM behavior and internal memory mapping differ between the two dies, even though the 256-BGA package is mechanically compatible. Always rebuild the linker script, validate the CPM interrupt vector table, and re-run bring-up tests when swapping an MPC860 for an MPC870 in a fielded design.
With the 256-BGA's 23x23 mm footprint and the 0-95C operating range, watch the junction temperature under continuous HDLC and Ethernet load. Place an array of thermal vias on the BGA's central ground balls and couple them to the inner ground plane; this typically keeps the die below 75C at typical office-ambient SOHO-router loads. For outdoor or industrial enclosures, do not exceed 85C measured case temperature - the headroom is intentionally narrow.
Informações de conformidade
RoHS compliant and Lead Free per DigiKey listing for this MPN. AEC-Q100 not applicable (industrial/commercial telecom). REACH, halogen-free, and conflict-minerals status not directly stated in the retrieved product page; consult NXP compliance documentation if your program requires these certifications.