MPC870CVR133 - 133MHz PowerQUICC MPC8xx MPU 256-BGA | NXP
MPN: MPC870CVR133 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $27.85 | $27.85 |
| 10 | $25.06 | $250.60 |
| 100 | $22.85 | $2,285.00 |
| 500 | $20.5 | $10,250.00 |
| 1,000 | $18.4 | $18,400.00 |
MPC870CVR133 Overview
Background Knowledge: A PowerQUICC (Quad Integrated Communications Controller) is a family of communications processors derived from Motorola's (now NXP/Freescale) Power Architecture line. The MPU (Microprocessor Unit) class combines a general-purpose integer core with a dedicated communications engine that handles DMA, serial protocols, and time-division multiplexing. Within the broader taxonomy it sits as: PowerQUICC -> communications processor -> embedded MPU -> 32-bit RISC processor -> semiconductor. Engineers choose PowerQUICC parts when they need deterministic protocol handling without burdening the host CPU with interrupt overhead.
Key feature highlights of the MPC870CVR133 include: 133 MHz core clock, 32-bit Power Architecture core, integrated CPM (Communications Processor Module), 26 MHz system bus, 32-bit data bus width, and 256-pin PBGA (23x23) package. The 'C' in the part number refers to the commercial -40 °C to +100 °C junction temperature grade; 'VR' indicates the part is supplied in tape-and-reel orientation (Tray in distributor packaging context). It is pin-compatible with the broader MPC8xx PowerQUICC family footprint for legacy board reuse.
Technical depth: The MPC870 integrates an 8 KB instruction cache, 8 KB data cache, MMU with hardware page translation, and the CPM coprocessor containing dual Fast Communication Controllers (FCC), two SCCs, two SMCs, an SPI, an I²C port, parallel ports, and a 4-channel DMA controller. The core runs at 133 MHz giving 176 MIPS at 4.5 V while consuming roughly 1.5 W typical (verification recommended against datasheet). The wide external bus (32-bit) supports SDRAM, SRAM, and ROM/Flash memory-mapped peripherals.
Typical applications of this MPU span networking and embedded communication roles: 10/100 Ethernet routers and bridges, DSL modems and residential gateways, ISDN terminal adapters, VoIP ATAs, networked printers with embedded protocol stacks, industrial serial-protocol bridges, and SCADA/remote telemetry controllers where deterministic serial handling matters.
Design consideration: The 256-ball PBGA requires a minimum of four PCB layers with controlled-impedance routing for the external bus; bypass capacitors must be placed as close as possible to each power/ground ball pair. Note that the MPC870 line is a legacy product and active new designs should consider the MPC8313, P1010, or QorIQ P1020 successors which offer modern interfaces (PCIe, GbE, USB) at lower power.
This page consolidates distributor pricing tiers, drop-in compatible MPC8xx-family alternatives, and design notes not duplicated on the manufacturer datasheet, including a comparison table against other 133 MHz and 50 MHz siblings to clarify the trade-offs when selecting replacement parts.
Drop-in alternatives for MPC870CVR133 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC870CVR133 (same form factor and footprint) — differing in Package, Core, Core Architecture, Operating Temperature, Data Bus Width.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MPC870VR133
✅ Drop-In✓ In Stock
$17.5 / Unit
View Datasheet →MPC870CVR133BGA
✅ Drop-In📋 Reference alternative (not in catalog)
MPC875CVR133
✅ Drop-In✓ In Stock
$43.75 / Unit
View Datasheet →MPC860SRCZQ66B
✅ Drop-In📋 Reference alternative (not in catalog)
MPC852TVR50A
✅ Drop-In✓ In Stock
$23.9 / Unit
View Datasheet →MPC870CVR133C
✅ Drop-In📋 Reference alternative (not in catalog)
MPC870CVR133 Maximum Ratings & Electrical Characteristics
| Manufacturer | NXP Semiconductors (formerly Freescale Semiconductor) |
| Series | PowerQUICC MPC8xx |
| Core | MPC8xx |
| Core Architecture | Power Architecture (32-bit RISC) |
| Maximum Clock Frequency | 133 MHz |
| Instruction Throughput | 176 MIPS |
| Data Bus Width | 32-bit |
| Number of Cores | 1 |
| Operating Supply Voltage | 3.3 V |
| Package | 256-BGA (PBGA, 23x23 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -40 °C to +100 °C (junction) |
| Temperature Grade | Commercial |
| Peripherals | CPM (FCC/SCC/SMC), DMA, Ethernet, UART, SPI, I²C |
| System Bus Frequency | 26 MHz (60x bus, internal core multiplier) |
MPC870CVR133 Pin Configuration
| Pin A1 | VDD — Core logic power supply |
| Pin B2 | IRQ_OUT — Interrupt request output |
| Pin C3 | TXD1/SMTXD1 — SMC transmit data |
| Pin D4 | RXD1/SMRXD1 — SMC receive data |
| Pin GND center | GND — Ground reference |
| Pin TDI | TDI — JTAG test data in |
| Pin TDO | TDO — JTAG test data out |
| Pin TCK | TCK — JTAG test clock |
| Pin TMS | TMS — JTAG test mode select |
| Pin TRST | TRST — JTAG test reset (active low) |
Typical Applications
MPC870CVR133 is suitable for 7 applications: 10/100 Ethernet Router / Bridge, DSL Modem and Residential Gateway, Industrial Serial Protocol Bridge, Networked Printer / Multifunction Device Controller, VoIP Analog Telephone Adapter (ATA), SCADA Remote Telemetry Unit (RTU), Automotive Telematics ECU.
10/100 Ethernet Router / Bridge
The MPC870CVR133's PowerQUICC core integrates an Ethernet MAC (FCC) and dedicated CPM that offloads 10/100 Mbps packet processing from the host CPU, while the 133 MHz core handles routing table lookups and control plane forwarding. Placed on the LAN/WAN side of small-office routers, the part can sustain wire-rate 100 Mbps bridging with hardware-only filtering via the CPM's independent RISC engine. The 32-bit bus and 26 MHz bus interface provide ample bandwidth for memory-mapped flash and SDRAM on the same board. Compared with discrete MCU + Ethernet PHY pairs, the MPC870CVR133 reduces interrupt load by orders of magnitude.
Recommended
DSL Modem and Residential Gateway
Residential gateways combine a DSL front-end with Ethernet and VoIP endpoints - exactly the workload the MPC870CVR133 is designed for. The CPM's FCC port handles ATM AAL5/PPP data pump functions, while the SCC/SMC ports drive VoIP DSPs and serial console. PowerQUICC determinism ensures TDM voice quality without jitter even when best-effort LAN traffic spikes. The 256-BGA package size accommodates 4-layer low-cost PCB designs typical of consumer premises equipment. Industrial-grade junctions to -40 °C support outdoor enclosures.
Recommended
Industrial Serial Protocol Bridge
Industrial plants run decades-old RS-232/RS-485 buses that modern controllers struggle to handle reliably. The MPC870CVR133's dual SCCs and SMCs support async/sync serial up to 50 Mbps with hardware framing, plus HDLC on the SCCs, satisfying gateway duty cycles between Modbus RTU, Profibus, and custom industrial protocols. The -40 °C to +100 °C junction temperature grade handles cabinet mounting, and the 32-bit bus cleanly bridges legacy peripherals to an Ethernet uplink. The CPM's independent RISC engine ensures deterministic latency regardless of CPU utilisation.
Recommended
Networked Printer / Multifunction Device Controller
Office MFPs require a controller that can move print data from Ethernet to a print engine at sustained rates, manage USB/scan workflows, and run the user interface. The MPC870CVR133's FCC Ethernet port handles MJPEG/PWG PDL reception while the SMCs drive the scanner CCD clocking and a UART communicates with the printing engine controller. The 8 KB instruction and 8 KB data caches accelerate PDL rasterisation bursts, and the 32-bit bus connects to a sizeable SDRAM for buffered print queues. Power-saving idle modes in the PowerQUICC allow energy-efficient USB sleep states.
Recommended
VoIP Analog Telephone Adapter (ATA)
ATAs connect POTS phones to VoIP providers by digitising voice, running RTP/tone conversion, and handling SIP/registration. The MPC870CVR133's SCC runs HDLC to PSTN-side processor and the Ethernet FCC passes RTP packets. PowerQUICC integration eliminates the need for a separate DSP for G.711 pass-through, given the 176 MIPS throughput. Sub-100 ms latency is achievable for typical one-call loads; multi-line devices are feasible but require DSP offload. The 256-BGA thermal envelope at this clock is under 1.5 W typical, easing thermal design in slim plastic housings.
Recommended
SCADA Remote Telemetry Unit (RTU)
SCADA RTUs in substations and pipeline networks require multi-port serial handling with deterministic response under burst conditions. The MPC870CVR133's CPM provides independent protocol processing on up to 2 FCCs and 2 SCCs, mapping cleanly to IEC 61850/Modbus/DNP3 master/slave nodes. Industrial temperature operation from -40 °C supports outdoor cabinets and unconditioned substation racks. The 32-bit external bus serves SDRAM for trend-log buffer storage; the watchdog timer and JTAG interface support compliance-grade diagnostics. The part's mature firmware ecosystem shortens NERC-CIP certification cycles.
Recommended
Automotive Telematics ECU
Although not the newest process, the MPC870CVR133's industrial temperature grade and CPM-based CAN/HW serial handling kept it deployed in some fleet telematics ECUs designed in the early 2000s. The PowerQUICC ensures deterministic CAN-style serialisation and integrates Ethernet for satellite backhaul. Designs that have completed OEM validation can rely on the device's known firmware behaviour; new projects should now target ARM Cortex-R/M-based automotive MCUs for active maintenance. The BGA package and pinout remain documented to support service-field repairs.
Recommended
Recommended Products Summary
Engineering reference data for MPC870CVR133 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC870VR133 | MPC870CVR133BGA | MPC875CVR133 | MPC860SRCZQ66B | MPC852TVR50A |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 256-BGA (PBGA, 23x23 mm) | 256-BGA (PBGA, 23x23 mm) - same | 256-BGA (PBGA, 23x23 mm) - same | 256-BGA (PBGA, 23x23 mm) - same | 256-BGA (PBGA, 23x23 mm) - same | 256-BGA (PBGA, 23x23 mm) - same |
| Maximum Clock Frequency | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 66 MHz | 50 MHz |
| Instruction Throughput | 176 MIPS | 176 MIPS | 176 MIPS | 176 MIPS | ~88 MIPS (66 MHz) | ~66 MIPS (50 MHz) |
| USB 2.0 Support | No | No | No | Yes (full-speed USB 2.0) | No | No |
| Data Bus Width | 32-bit | 32-bit | 32-bit | 32-bit | 32-bit | 32-bit |
| Operating Temperature Range | -40 °C to +100 °C (junction) | -40 °C to +100 °C | -40 °C to +100 °C | -40 °C to +100 °C | -40 °C to +105 °C | -40 °C to +100 °C |
| Lifecycle Status | NRND | NRND | NRND | NRND | EOL (last-time-buy) | NRND |
Key Differentiators
- Highest-integration 133 MHz part with full CPM (vs MPC860SRCZQ66B)
- PowerQUICC CPM offload of serial protocol handling (vs MPC852TVR50A)
- USB-equipped variant on same footprint (vs MPC875CVR133)
Design Notes
The 256-BGA package demands a minimum 4-layer PCB with dedicated VDD and GND planes on inner layers to provide low-impedance power delivery. Use 0.1 µF and 10 µF decoupling capacitors within 50 mil of each power ball pair; via stitching of GND balls to the inner ground plane is critical for returning high-frequency CPM noise. PBGA collapse distance tolerance is ±2 mil, requiring precise solder paste printing and reflow with peak ≤260 °C for RoHS profiles. Use 1.27 mm pitch pads with NSMD (non-solder mask defined) lands for best stand-off and rework capability.
At 133 MHz the typical core power is roughly 1.5 W; in enclosed cabinets with no airflow, junction-to-ambient thermal resistance of ~25 °C/W implies a ΔT of 37 °C above ambient. Confirm that the chosen PCB layout and enclosure allow the temperature to stay within the -40 °C to +100 °C rated junction. For high-DMIPS loads running continuously, derate by 25 % or add passive airflow. Always place thermistor-bearing supply packages away from hot spots.
Estimated: the system bus operates at 26 MHz - configure the SIU configuration registers to set the bus-to-core ratio correctly (1:1, 2:1, 3:1, or more common 5:1 for 130 MHz), or the firmware will hang on first boot. Do NOT forget the BSYNCRESET sequence on PLL programming: typical MPC8xx firmware will lock without proper configuration. Always engage the JTAG debugger during bring-up; the BGA prevents probing otherwise. Update to the latest CPM microcode patch from NXP/Freescale for known errata.
Compliance Information
RoHS and REACH compliance per NXP product declarations. The 256-BGA package uses lead-free solder balls. Not AEC-Q100 qualified - automotive designs should consult NXP automotive-grade derivatives. NRND status as of 2026-10-17.
