SI5335C-B07520-GM - 4-Output Clock Generator, 350 MHz, QFN-24 | Skyworks
N.º da peça: SI5335C-B07520-GM ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $6.45 | $6,45 |
| 10 | $5.78 | $57,80 |
| 100 | $5.12 | $512,00 |
| 500 | $4.61 | $2.305,00 |
| 1.000 | $4.05 | $4.050,00 |
SI5335C-B07520-GM Visão geral
A clock generator IC (also called a frequency synthesizer or clock multiplier) is a timing device that derives one or more precise output frequencies from a single low-frequency reference source such as a crystal or oscillator. Within the broader IC taxonomy it sits under Clock & Timing ICs -> Clock Generator -> Timing IC -> Power Management and Signal Chain IC. Modern clock generators like the Si5335 family integrate PLLs with fractional-N dividers (MultiSynth) to produce arbitrary non-integer-related frequencies without the spurs typical of integer-N synthesizers, replacing legacy solutions built from discrete PLL + VCXO + divider chains.
Key differentiating specifications include four independently-programmable output banks, output frequency range of 1 MHz to 350 MHz, low typical RMS phase jitter of sub-ps on select frequencies, integrated 2.5 V or 3.3 V LDO regulators permitting single 1.8 V / 2.5 V / 3.3 V supply operation, and five user-defined pins (pins 3, 5, 6, 12, 19) that the ClockBuilder Pro utility can customize for functions such as OE, FS, SS, PD, or frequency select. The exposed thermal pad of the QFN-24 package provides a low theta_JA thermal path for reliable operation across -40C to +85C ambient. The IC also features configurable spread-spectrum capability for EMI mitigation in consumer and industrial designs.
The Si5335C architecture pairs a high-frequency integer PLL with four independent MultiSynth fractional output dividers, allowing each output to have a unique frequency unrelated to the others by any integer ratio. This is critical for systems that require CPU clock, DDR memory clock, PCIe reference clock, and an audio or video clock from a single device. The internal LDOs isolate the analog PLL supply from the noisy digital output supply, contributing to the part's strong jitter performance.
Typical applications include networking switches and routers, FPGA-based designs (Xilinx 7-series, Intel Cyclone, Lattice ECP5), telecom base-station timing, multi-rate audio/video broadcast equipment, server and storage controller boards, and test-and-measurement instrumentation. When laying out the Si5335C, place the reference input crystal or LVCMOS source within 5 mm of the REF input pin, route each differential output pair with matched 100 ohm differential microstrip or stripline, and stitch the exposed pad with at least 9 thermal vias for low ground impedance. The datasheet recommends 0.1 uF decoupling close to each VDD pin and a 1 uF bulk capacitor near the exposed pad. This page consolidates distributor pricing, drop-in alternatives, and PCB design notes not found in a single point in the manufacturer datasheet.
Alternativas drop-in para SI5335C-B07520-GM — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com SI5335C-B07520-GM (mesmo formato e footprint) — diferindo em Number of Outputs, Output Frequency Range, Package, Core Supply Voltage, MSL Level.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SI5335C-B07520-GMR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5335B-B10210-GM
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$8.5 / unidade
Ver ficha técnica →SI5335B-B03900-GMR
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$3.48 / unidade
Ver ficha técnica →SI5335C-B07521-GM
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
SI5335C-B07520-GM Especificações
| Função | Clock generator |
| Número de saídas | 4 |
| Tipo de saída | Differential or single-ended (CMOS, LVDS, HCSL, LVPECL) |
| Output Frequency Range | 1 MHz to 350 MHz |
| Input Type | Crystal, LVCMOS, LVDS, LVPECL, HCSL reference |
| Number of Input References | 1 |
| Tensão de alimentação | 1.8 V / 2.5 V / 3.3 V (single supply) |
| Internal LDOs | Yes (2.5 V/3.3 V core LDO) |
| Programmability | Web-customizable via ClockBuilder Pro utility |
| User-Defined Pins | 5 (pins 3, 5, 6, 12, 19) |
| Spread Spectrum | Configurable (down-spread and center-spread) |
| Output Enable Control | Per-bank OE (hardware-managed via pin) |
| Encapsulamento | 24-VFQFN Exposed Pad (QFN-24, 4x4 mm) |
| Tipo de montagem | Surface Mount |
| Temperatura de operação | -40C to +85C |
| Nível MSL | 2 (1 year floor life) |
| Status RoHS | Compliant |
| Packaging | Tray (GM suffix) |
Configuração de pinos do SI5335C-B07520-GM
| Pino 1 | CLK0A — Output clock bank 0, channel A (format factory-configured) |
| Pino 2 | CLK0B — Output clock bank 0, channel B (format factory-configured) |
| Pino 3 | USER_DEF_1 — User-defined pin (OE/FS/SS/PD function per ClockBuilder Pro) |
| Pino 4 | VDD — Digital supply voltage (1.8 V / 2.5 V / 3.3 V) |
| Pino 5 | USER_DEF_2 — User-defined pin (OE/FS/SS/PD function per ClockBuilder Pro) |
| Pino 6 | USER_DEF_3 — User-defined pin (OE/FS/SS/PD function per ClockBuilder Pro) |
| Pino 7 | VDD — Digital supply voltage (1.8 V / 2.5 V / 3.3 V) |
| Pino 8 | CLK1A — Output clock bank 1, channel A (format factory-configured) |
| Pino 9 | CLK1B — Output clock bank 1, channel B (format factory-configured) |
| Pino 10 | GND — Ground |
| Pino 11 | VDD — Digital supply voltage (1.8 V / 2.5 V / 3.3 V) |
| Pino 12 | USER_DEF_4 — User-defined pin (OE/FS/SS/PD function per ClockBuilder Pro) |
| Pino 13 | CLK2A — Output clock bank 2, channel A (format factory-configured) |
| Pino 14 | CLK2B — Output clock bank 2, channel B (format factory-configured) |
| Pino 15 | GND — Ground |
| Pino 16 | VDD — Digital supply voltage (1.8 V / 2.5 V / 3.3 V) |
| Pino 17 | CLK3A — Output clock bank 3, channel A (format factory-configured) |
| Pino 18 | CLK3B — Output clock bank 3, channel B (format factory-configured) |
| Pino 19 | USER_DEF_5 — User-defined pin (OE/FS/SS/PD function per ClockBuilder Pro) |
| Pino 20 | VDD — Digital supply voltage (1.8 V / 2.5 V / 3.3 V) |
| Pino 21 | XIN/REF — Crystal input or external reference input |
| Pino 22 | XOUT — Crystal output (leave NC if external reference used) |
| Pino 23 | GND — Ground |
| Pino 24 | VDD — Digital supply voltage (1.8 V / 2.5 V / 3.3 V) |
Aplicações típicas
SI5335C-B07520-GM é adequado para 6 aplicaçãos: FPGA Reference Clock Tree, Networking Switch and Router Timing, Telecom Base Station Timing, Server and Storage Controller Boards, Broadcast Audio/Video Equipment, Test and Measurement Instrumentation.
FPGA Reference Clock Tree
The SI5335C-B07520-GM is well suited as a single-IC reference clock tree for Xilinx 7-series, Intel Cyclone V, and Lattice ECP5 FPGA designs that need four independent clocks - system clock, DDR memory clock, PCIe reference clock, and a transceiver reference. Its 350 MHz output ceiling covers the most common FPGA fabric, GT transceiver, and memory-controller clock frequencies from one part, while the four MultiSynth dividers let each output be a non-integer-related frequency. Placed near the FPGA clock input pins with matched-length traces, the Si5335C's sub-ps RMS jitter satisfies PCIe Gen2/3 and GbE jitter masks, replacing legacy solutions built from a PLL plus VCXO plus multiple dividers with a single 4x4 mm QFN-24 device.
Recomendado
Networking Switch and Router Timing
Networking switches and routers typically require multiple unrelated clocks for the management CPU, PHY reference, packet processor, and timing-over-packet logic, and the SI5335C-B07520-GM delivers all four from a single reference. Per the Skyworks datasheet, the four MultiSynth outputs can each be set to common Ethernet rates (25 MHz, 50 MHz, 100 MHz, 125 MHz, 156.25 MHz, 161.13 MHz) without external VCXOs, and the integrated LDOs reject switching-converter noise on the same PCB. The -40C to +85C industrial temperature range suits outdoor and indoor switch deployments, while the QFN-24 footprint fits within the tight board real-estate of compact 1G/10G switch designs.
Recomendado
Telecom Base Station Timing
Wireless base-station baseband boards require stable, low-jitter clocks at multiple rates - typically a baseband DSP clock, a CPRI/SERDES reference, a timing-card synchronization clock, and a local oscillator - and the SI5335C-B07520-GM supplies all four from one factory-programmed device. Its low RMS phase jitter (sub-ps on common frequencies) satisfies 3GPP base-station clock-purity requirements, and the configurable spread-spectrum option reduces EMI in dense multi-board chassis. Placed near the baseband ASIC with each output routed with controlled-impedance differential pairs, the Si5335C replaces a stack of discrete PLL + crystal + divider ICs with a single 4x4 mm device that operates from -40C to +85C.
Recomendado
Server and Storage Controller Boards
Enterprise server and storage controller boards (RAID HBAs, NVMe controllers, SATA/SAS expanders) require multiple precise clocks for the host interface, memory subsystem, and on-board PHY, and the SI5335C-B07520-GM provides four independent clocks from a single reference. Its 1.8 V / 2.5 V / 3.3 V single-supply operation simplifies the BOM, and the four user-defined pins (pins 3, 5, 6, 12, 19) can be configured for per-output enable, spread-spectrum on/off, and frequency-select controls needed for SAS/SATA power-management states. The QFN-24 exposed pad provides the thermal headroom needed in confined server backplanes running at elevated ambient temperatures.
Recomendado
Broadcast Audio/Video Equipment
Professional broadcast audio/video routers and format converters need multiple unrelated clocks at audio (48 kHz x 256 = 12.288 MHz, 24.576 MHz, 49.152 MHz), video (27 MHz, 74.25 MHz, 148.5 MHz for HD/3G/12G-SDI), and processing rates - exactly the use case the SI5335C-B07520-GM targets. Its MultiSynth fractional dividers can synthesize each of these unrelated rates from a single low-frequency reference without external VCXOs, and the configurable output formats (LVDS, LVPECL, HCSL, CMOS) drive both audio DACs and SDI serializers directly. The exposed-pad QFN-24 keeps the BOM small enough to fit on daughter cards inside 1U rack frames.
Recomendado
Test and Measurement Instrumentation
Test-and-measurement instruments (oscilloscopes, spectrum analyzers, protocol analyzers) need many unrelated low-jitter clocks at ADC sample rates, FPGA fabric rates, display rates, and trigger rates, and the SI5335C-B07520-GM delivers four independent clocks from a single 1.8 V-3.3 V supply. Its sub-ps RMS jitter keeps ADC SNR high, the four user-defined pins can be used for frequency-select switching between test modes, and the -40C to +85C range supports lab and field-instrument environments. Placed adjacent to the ADC and FPGA clock pins with controlled-impedance routing, the Si5335C replaces multi-IC clock trees with a single factory-programmed device.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SI5335C-B07520-GM — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SI5335C-B07520-GMR | SI5335B-B10210-GM | SI5335B-B03900-GMR | SI5335C-B07521-GM |
|---|---|---|---|---|---|
| Brand | Skyworks (formerly Silicon Labs) | Skyworks (formerly Silicon Labs) | Skyworks (formerly Silicon Labs) | Skyworks (formerly Silicon Labs) | Skyworks (formerly Silicon Labs) |
| Package | QFN-24 (4x4 mm) exposed pad | QFN-24 (4x4 mm) - same | QFN-24 (4x4 mm) - same | QFN-24 (4x4 mm) - same | QFN-24 (4x4 mm) - same |
| Number of Outputs | 4 | 4 | 4 | 4 | 4 |
| Max Output Frequency | 350 MHz | 350 MHz | 200 MHz | 200 MHz | 350 MHz |
| Programmability | Factory via ClockBuilder Pro | Factory via ClockBuilder Pro | Factory via ClockBuilder Pro | Factory via ClockBuilder Pro | Factory via ClockBuilder Pro |
| Supply Voltage | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V |
| Packaging Carrier | Tray (GM) | Tape & Reel (GMR) | Tray (GM) | Tape & Reel (GMR) | Tray (GM) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS / Lead-Free | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes |
Principais diferenciais
- Highest output frequency in the Si5335 family (vs SI5335B-B10210-GM)
- Same factory-programmed frequency plan in different carrier (vs SI5335C-B07520-GMR)
- Factory customization eliminates external VCXOs (vs Discrete PLL + VCXO + divider solution)
Notas de projeto
Per the Skyworks Si5335 datasheet, place the reference input crystal (or LVCMOS/LVDS reference source) within 5 mm of the XIN/REF pin (pin 21), route differential output pairs (CLKxA/CLKxB) with matched-length traces using 100 ohm differential impedance, and stitch the exposed pad (EP) with at least 9 thermal vias in a 3x3 grid for low-impedance ground and thermal relief. Keep digital output traces away from the XIN/REF input to avoid coupling noise back into the PLL.
Per the Skyworks Si5335 datasheet, place one 0.1 uF decoupling capacitor within 1 mm of each VDD pin and one 1 uF bulk capacitor adjacent to the exposed pad. The Si5335C integrates internal LDOs that derive the analog PLL supply from the VDD input, so a clean external supply is essential: ripple above 50 mVpp on VDD can couple into the PLL and degrade jitter. Avoid sharing VDD traces with high-current switching nodes.
Do not assume the SI5335C-B07520-GM pinout is fixed: pins 3, 5, 6, 12, and 19 are user-defined functions whose exact role (OE, FS, SS, PD, frequency select) is set per part number by ClockBuilder Pro. Always reference the datasheet addendum or your ClockBuilder Pro project export for the specific MPN suffix you ordered. Also, the SI5335B family has a 200 MHz output ceiling - do not substitute SI5335B for SI5335C designs that require >200 MHz output.
Each output bank can be factory-configured as CMOS, LVDS, LVPECL, HCSL, or a custom format. When using differential outputs (LVDS/LVPECL/HCSL), route each pair with 100 ohm differential impedance and maintain length matching within 5 mil (0.13 mm) to preserve duty cycle and reduce EMI. Terminate outputs per the format-specific guidance in AN408 - LVDS with 100 ohm across the pair, LVPECL with 150 ohm to GND on each line, HCSL with 33 ohm series and 50 ohm to GND.
Informações de conformidade
RoHS compliant per Skyworks/SiLabs product page. Not AEC-Q100 qualified - this is a commercial/industrial grade clock generator intended for -40C to +85C ambient operation. Lead-free (Pb-free) matte-tin finish.
