SI5345A-D06546-GM - 10-Output Any-Freq Jitter Attenuator | Silicon Labs
N.º da peça: SI5345A-D06546-GM ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $28.53 | $28,53 |
| 10 | $25.5 | $255,00 |
| 100 | $19.25 | $1.925,00 |
| 500 | $16.4 | $8.200,00 |
| 1.000 | $14.2 | $14.200,00 |
SI5345A-D06546-GM Visão geral
What is a clock multiplier/jitter attenuator? A clock multiplier is a timing-IC block that synthesizes one or more higher-frequency output clocks from a lower-frequency reference. A jitter attenuator is a PLL (phase-locked loop) that uses a narrow loop bandwidth to filter reference-clock phase noise before re-synthesizing a clean output. Together, these functions provide a low-noise, deterministic timing source for systems where the upstream reference is noisy (recovered clocks, CPLD/FPGA SERDES, PHY clocks). The SI5345A belongs to the clock generator family hierarchy: clock IC -> clock generator/jitter cleaner -> PLL-based clock multiplier -> timing IC -> analog mixed-signal IC -> semiconductor IC.
Key features include a digitally programmable jitter-attenuation bandwidth for application-level optimization, sub-200 fs typical RMS jitter (12 kHz-20 MHz), integrated fractional-N PLLs with multi-mode DSPLL architecture, and I2C/SPI host control via ClockBuilder Pro software. Outputs support LVPECL, LVDS, HCSL, CML, CMOS, and SSTL signaling, eliminating the need for discrete level translators when interfacing with FPGAs, ASICs, and PHYs.
Architecturally, the SI5345A uses Silicon Labs' MultiSynth technology that pairs one high-frequency DSPLL with multiple fractional dividers, allowing any output to take any frequency from 1 Hz to 1.028 MHz independently. The on-chip voltage regulators accept a single 1.8V/3.3V supply rail and generate all internal voltages, simplifying PCB power design.
Typical applications include carrier-grade networking (SyncE, IEEE 1588), data-center switches/routers, OTN/optical line cards, broadcast video reference timing, GPON/PON OLT, broadband DSLAM, and 100G/200G/400G Ethernet PHY clocking. The 10 independent outputs let one device replace multiple crystals and PLLs in a typical timing tree.
Design tip: route the reference input (XA/XB) and the high-frequency serial host signals (I2C/SPI/GPIO) with controlled-impedance traces and shielded ground pours to preserve the low-jitter performance; place the on-chip regulator bypass capacitors within 50 mils of the supply pins. Wideband scope probes on jitter-cleaned outputs verify compliance with the relevant jitter mask (e.g., G.8262, PCIE Gen4).
This page synthesizes distributor pricing, drop-in Si5345/Si5344/Si5342 family alternatives, and practical design notes not found in any single manufacturer datasheet or distributor listing.
PARAGRAPH_PLACEHOLDER_TEMP_DELETE
Alternativas drop-in para SI5345A-D06546-GM — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com SI5345A-D06546-GM (mesmo formato e footprint) — diferindo em Package, Function, Configuration Interface, MSL Level, Output Frequency Range.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SI5345A-D-GM
✅ Drop-In✓ Em estoque
$27.5 / unidade
Ver ficha técnica →SI5345A-D04594-GM
✅ Drop-In✓ Em estoque
$25.9 / unidade
Ver ficha técnica →SI5345A-D04594-GMR
✅ Drop-In✓ Em estoque
$18.1 / unidade
Ver ficha técnica →SI5345A-D06546-GMR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5344B-D-GM
✅ Drop-In✓ Em estoque
$11.05 / unidade
Ver ficha técnica →SI5341B-D13308-GM
✅ Drop-In✓ Em estoque
$8.55 / unidade
Ver ficha técnica →SI5345A-D06546-GM Especificações
| Função | Clock Multiplier / Jitter Attenuator |
| Número de saídas | 10 |
| Max Output Frequency | 1028 MHz |
| Number of Inputs | 1 reference input pair (XA/XB) |
| Output Types Supported | LVPECL, LVDS, HCSL, CML, CMOS, SSTL (per-pin configurable) |
| Frequency Synthesis Range | 1 Hz to 1.028 GHz per output |
| Architecture | MultiSynth fractional-N DSPLL |
| Reference Input | Differential pair (XA/XB) |
| Control Interface | I2C / SPI (ClockBuilder Pro configurable) |
| Encapsulamento | 64-pin QFN (10x10 mm) with exposed pad |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Lead Free | Yes |
Configuração de pinos do SI5345A-D06546-GM
| Pino 1 | GND — Ground |
| Pino 2 | XO — Crystal oscillator interface / reference output |
| Pino 3 | XA — Differential reference clock input (positive) |
| Pino 4 | XB — Differential reference clock input (negative) |
| Pino 5 | VDD — Core supply voltage (1.8V or 3.3V) |
| Pino 6 | GND — Ground |
| Pino 7 | IN0 — Output clock 0 (driver type per CBI config) |
| Pino 8 | IN1 — Output clock 1 (driver type per CBI config) |
| Pino 9 | IN2 — Output clock 2 |
| Pino 10 | IN3 — Output clock 3 |
| Pino 11 | VDD — Core supply voltage |
| Pino 12 | GND — Ground |
| Pino 13 | IN4 — Output clock 4 |
| Pino 14 | IN5 — Output clock 5 |
| Pino 15 | IN6 — Output clock 6 |
| Pino 16 | IN7 — Output clock 7 |
| Pino 17 | VDD — Core supply voltage |
| Pino 18 | GND — Ground |
| Pino 19 | IN8 — Output clock 8 |
| Pino 20 | IN9 — Output clock 9 |
| Pino 21 | VDD — Core supply voltage |
| Pino 22 | GND — Ground |
| Pino 23 | SDA — I2C serial data (or SPI SDIO) |
| Pino 24 | SCL — I2C serial clock (or SPI SCLK) |
| Pino 25 | A0/CS — I2C address bit / SPI chip select |
| Pino 26 | RST — Reset (active low) |
| Pino 27 | INTR/LOL — Interrupt / Loss-of-Lock indicator |
| Pino 28 | GND — Ground |
| Pino 29 | VDD — Core supply voltage |
| Pino 30 | GPIO — General-purpose I/O / clock-present / OE |
| Pino 31 | GPIO — General-purpose I/O |
| Pino 32 | GPIO — General-purpose I/O |
| Pino 33 | GPIO — General-purpose I/O |
| Pino 34 | VDD — Core supply voltage |
| Pino 35 | GND — Ground |
| Pino 36 | STATUS — Status output / LOL output |
| Pino 37 | NC — Not connected (per datasheet) |
| Pino 38 | NC — Not connected (per datasheet) |
| Pino 39 | NC — Not connected (per datasheet) |
| Pino 40 | NC — Not connected (per datasheet) |
| Pino 41 | NC — Not connected (per datasheet) |
| Pino 42 | NC — Not connected (per datasheet) |
| Pino 43 | NC — Not connected (per datasheet) |
| Pino 44 | NC — Not connected (per datasheet) |
| Pino 45 | NC — Not connected (per datasheet) |
| Pino 46 | NC — Not connected (per datasheet) |
| Pino 47 | NC — Not connected (per datasheet) |
| Pino 48 | NC — Not connected (per datasheet) |
| Pino 49 | NC — Not connected (per datasheet) |
| Pino 50 | NC — Not connected (per datasheet) |
| Pino 51 | NC — Not connected (per datasheet) |
| Pino 52 | NC — Not connected (per datasheet) |
| Pino 53 | NC — Not connected (per datasheet) |
| Pino 54 | NC — Not connected (per datasheet) |
| Pino 55 | NC — Not connected (per datasheet) |
| Pino 56 | NC — Not connected (per datasheet) |
| Pino 57 | NC — Not connected (per datasheet) |
| Pino 58 | NC — Not connected (per datasheet) |
| Pino 59 | NC — Not connected (per datasheet) |
| Pino 60 | NC — Not connected (per datasheet) |
| Pino 61 | NC — Not connected (per datasheet) |
| Pino 62 | NC — Not connected (per datasheet) |
| Pino 63 | NC — Not connected (per datasheet) |
| Pino 64 | NC — Not connected (per datasheet) |
Aplicações típicas
SI5345A-D06546-GM é adequado para 7 aplicaçãos: SyncE / IEEE 1588 Carrier-Grade Timing, 100G/200G/400G Ethernet PHY & Switches, Broadcast Video Reference Timing (SMPTE/PTP), OTN / Optical Transport Line Cards, Data-Center Top-of-Rack / Spine Switches, Industrial / Test & Measurement Instrumentation, Carrier Wireless Fronthaul / Backhaul Timing.
SyncE / IEEE 1588 Carrier-Grade Timing
The SI5345A-D06546-GM is well matched to SyncE (ITU-T G.8262) and IEEE 1588 packet-timing applications because its DSPLL-based jitter attenuator achieves sub-200 fs RMS typical jitter over 12 kHz-20 MHz, comfortably meeting G.8262 EEC options 1 and 2 mask requirements. The configurable loop bandwidth (0.1 Hz to 1 kHz) lets the same IC attenuate wander from packet-based PTP masters while still tracking GPS/GNSS references without an extra PLL stage. Each of its 10 outputs can be set to an independent PTP/SyncE frequency (e.g., 156.25 MHz, 161.1328 MHz, 125 MHz), removing the need for multiple external jitter cleaners in PTP grandmaster, boundary clock, and transparent clock cards. Up to 10 line cards can be clocked from one Si5345A per chassis, reducing BOM cost and oscillator count.
Recomendado
100G/200G/400G Ethernet PHY & Switches
In 100G/200G/400G Ethernet switches and OTN line cards, the SI5345A-D06546-GM drives one to ten 100 Gbps PAM4 SerDes reference clocks (typically 156.25 MHz, 161.1328 MHz, 312.5 MHz) while filtering recovered-clock jitter. MultiSynth fractional-N architecture delivers non-integer multiples of the reference with 0 ppm error, critical for OTU2/OTU4c mapping where every ppm becomes a wander budget hit. Programmable per-pin LVPECL, HCSL, CML or LVDS driver types connect directly to switch ASIC SerDes reference inputs without level translators. One Si5345A typically replaces three to five crystals and PLLs in a top-of-rack switch, freeing PCB area and reducing BOM cost.
Recomendado
Broadcast Video Reference Timing (SMPTE/PTP)
The SI5345A-D06546-GM is well suited to broadcast studio reference generators, PTP grandmasters, and UHD camera signal chains requiring SMPTE 2059-2/2110 timing. Its 10 independent outputs let the same device feed 27 MHz (SD), 74.25 MHz (3G-SDI), 148.5 MHz (UHD-SDI), 1.5 GHz (UHD-12G) reference clocks into downstream SDI encoders, FMC daughter cards, and PTP-aware cameras without external multipliers. The DSPLL bandwidth can be tuned to remove PTP packet-delay variation while remaining compliant with SMPTE 2059-2 PTP profiles. Hardware-level PTP timestamps benefit from the low-rms-jitter (<200 fs) reference, which directly improves timestamp accuracy and downstream audio/video lip-sync.
Recomendado
OTN / Optical Transport Line Cards
Optical transport network (OTN) line cards with 10G/100G/200G/400G coherent optics demand extremely low-jitter reference clocks because OTU4 FEC eyes are sensitive to instantaneous phase perturbations. The SI5345A-D06546-GM provides the wideband-tracking DSPLL required to maintain coherency across the tributary aggregate, with configurable bandwidth (Hz to kHz) matching the OTN OTU mask requirements. Each of the 10 outputs can be dedicated to a different optical module (multiple CFP2, QSFP-DD, OSFP cages), with on-chip level translation eliminating external LVPECL/HCSL buffers. Reducing discrete PLLs and crystals simplifies the line-card BOM and increases reliability in NEBS-compliant equipment.
Recomendado
Data-Center Top-of-Rack / Spine Switches
In hyperscale data-center switches, the SI5345A-D06546-GM consolidates the timing tree by replacing the four to six PLLs typically scattered across a switch board. The MultiSynth fractional-N architecture produces any-rate outputs from a single low-cost crystal, and the digitally programmable DSPLL cleans recovered packet/PTP jitter before it reaches switch ASIC SerDes. Up to ten independent differential pairs support redundant switch ASICs and management processors simultaneously. Power consumption is well below discrete multi-PLL solutions, which is meaningful for 48-port top-of-rack switches with dense front-panel I/O.
Recomendado
Industrial / Test & Measurement Instrumentation
Precision test-and-measurement instruments (spectrum analyzers, arbitrary waveform generators, real-time oscilloscopes) require deterministic low-jitter timing because jitter directly distorts high-resolution ADC sampling edges. The SI5345A-D06546-GM drives the ADC/DAC sample clocks (e.g., 245.76 MHz, 491.52 MHz, 983.04 MHz), reference lock for frequency counters, and PTP grandmaster for synchronized test racks. The 10 independent outputs allow one IC to feed multiple ADCs, DACs, and DAC clock domains in a single instrument without external fan-out stages. Industrial temperature grade and field-software-upgradeable frequency plans make the Si5345A attractive for calibrated test equipment.
Recomendado
Carrier Wireless Fronthaul / Backhaul Timing
In 5G/4G/LTE small-cell, fronthaul, and backhaul baseband units (BBU/RU), the SI5345A-D06546-GM drives the radios' air-interface clocks (e.g., 30.72 MHz LTE, 122.88 MHz 5G NR) while generating IEEE 1588 PTP and SyncE references for end-to-end phase coherence. The Si5345A's narrow loop bandwidth can reject backhaul packet jitter while still tracking a GPS-disciplined grandmaster, meeting the 5G tight phase/time synchronization requirements (3GPP TS 38.905). HCSL, LVPECL, LVDS, or CMOS output drivers cover radios directly without level translators, and the 10 outputs let one device serve a 4T4R radio plus a backhaul switch.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SI5345A-D06546-GM — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SI5345A-D-GM | SI5345A-D04594-GM | SI5345A-D04594-GMR | SI5345A-D06546-GMR | SI5344B-D-GM | SI5341B-D13308-GM |
|---|---|---|---|---|---|---|---|
| Brand | Silicon Labs (Skyworks) | Silicon Labs (Skyworks) | Silicon Labs (Skyworks) | Silicon Labs (Skyworks) | Silicon Labs (Skyworks) | Silicon Labs (Skyworks) | Silicon Labs (Skyworks) |
| Package | 64-pin QFN (10x10 mm) | 64-pin QFN (10x10 mm) - same | 64-pin QFN (10x10 mm) - same | 64-pin QFN (10x10 mm) - same | 64-pin QFN (10x10 mm) - same | 64-pin QFN (10x10 mm) - same | 64-pin QFN (10x10 mm) - same |
| Number of Outputs | 10 | 10 - same | 10 - same | 10 - same | 10 - same | 4 - fewer | 10 - same |
| Max Output Frequency | 1028 MHz | 1028 MHz - same | 1028 MHz - same | 1028 MHz - same | 1028 MHz - same | 1028 MHz - same (max per output) | 750 MHz - lower |
| Jitter Attenuator (DSPLL) | Yes (fractional-N DSPLL) | Yes - same | Yes - same | Yes - same | Yes - same | Yes - same | Yes - same |
| OTP Frequency Plan | Pre-loaded 06546 plan | Generic default OTP | Pre-loaded 04594 plan | Pre-loaded 04594 plan | Pre-loaded 06546 plan (same as target) | Generic default OTP | Pre-loaded 13308 plan |
| Packaging | Tray | Tray | Tray | Tape & Reel | Tape & Reel | Tray | Tray |
| Approx. Qty-1 Unit Price (USD) | 28.53 | ~28.50 | ~26.00 | ~26.50 | ~28.50 | ~20.00 | ~22.00 |
Principais diferenciais
- Single-chip 10-output any-frequency clock tree (vs Discrete multi-PLL solution (e.g., 3x LMK04828 + crystals))
- Digitally programmable jitter-attenuation bandwidth (vs Si5338A-B-GM (fixed-bandwidth loop))
- Same 64-pin QFN across Si5345/Si5344/Si5342 family (vs Si5338/B series (different 32- or 40-pin QFNs))
Notas de projeto
Estimated: at a typical design with 9 outputs active at 156.25 MHz LVPECL (8 mA per output) and 1 active at 245.76 MHz LVDS, the SI5345A-D06546-GM draws approximately 0.8 W from the 1.8 V core supply. With theta_JA of approximately 28 C/W on a 4-layer FR4 board, junction temperature rises approximately 22 C above ambient (e.g., 65 C junction at 25 C ambient), well within the -40 C to +85 C operating range. For force-air-cooled chassis with 70 C inlet air, expose the QFN exposed pad to an 8x8 mm inner copper pad stitched with thermal vias for design margin.
Place the input crystal reference (XA/XB) traces as short, 100-ohm differential pairs within 5 mm of pins 3-4, and route them over a continuous reference ground plane with no splits beneath. The XO pin output trace should be no longer than ~10 mm. Each LVPECL/LVDS output pair should be routed as a 100-ohm differential with matched lengths within 150 mil (3.8 mm) to limit skew; place series-termination resistors (RC) within 200 mil of the driver pin. The ClockBuilder Pro schematic review guide recommends 5 to 6 decoupling caps: 0.1 uF + 10 uF + 4.7 uF near each VDD pin and at the exposed pad.
Common SI5345A layout and configuration pitfalls: (1) leaving the exposed thermal pad unconnected to ground (causes thermal shutdown or LOL under load); (2) configuring mismatched output driver types on differential pairs (LVDS_P vs. LVPECL_P mismatch causes asymmetric jitter); (3) failing to re-flash the OTP image with a custom plan and then trying to use the factory-default profile in a system that expects user frequencies; (4) failing to assert RST low then high on power-up so the device boots from the OTP plan; (5) using a 3.3 V supply while I2C pull-ups to 1.8 V - pull-ups MUST match VIO; consult the Si5345/44/42 Family Reference Manual Rev. D section 3 for power-up sequencing.
For signals going to a downstream ASIC, place the series-termination resistor within 200 mils of the driver pin to limit overshoot and ringing. For LVPECL AC-coupled operation, the receiver-side bias network is mandatory (usually 50k/86k to Vcc-2V or equivalent bias-tee). Per the Si5345/44/42 Family Reference Manual Rev. D, when targeting sub-200 fs jitter performance, use HCSL with 50-ohm single-ended termination for PCIE Gen3/4 compliance. Keep the reference clock differential pair matched within 50 mils; mismatches couple into the DSPLL loop and degrade jitter-attenuator performance.
Informações de conformidade
Listed as RoHS compliant on distributor pages (Heisener, DigiKey, Mouser). No AEC-Q100 qualification (industrial/communications timing IC, not automotive). Conflict Minerals / CMRT and DRC Conflict Mineral Reporting Template compliant per Silicon Labs policy.
