SI5345A-D04594-GMR - 10-Output Jitter Attenuator | Skyworks
N.º da peça: SI5345A-D04594-GMR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $28.5 | $28,50 |
| 10 | $25.65 | $256,50 |
| 100 | $22.8 | $2.280,00 |
| 500 | $19.95 | $9.975,00 |
| 1.000 | $18.1 | $18.100,00 |
SI5345A-D04594-GMR Visão geral
A clock synthesizer (sometimes called a clock generator or frequency synthesizer) is an IC that derives one or more precise output frequencies from a single reference source. Within the broader hierarchy, the SI5345A belongs to the clock timing IC family, which sits under integrated circuits and plays a critical role in synchronous digital systems: SOC > integrated circuit > clock & timing IC > clock generator > frequency synthesizer > jitter attenuator. Jitter attenuators add a low-bandwidth PLL on top of a synthesizer to filter reference-clock noise before redistribution to downstream PHYs, ADCs, DACs, and FPGAs.
Key features of this variant include ten independently configurable output formats (LVDS, LVPECL, HCSL, CML, CMOS, HSTL, SSTL), an I2C control interface, 1.71 V to 1.89 V core supply range, and a -40 C to +85 C industrial operating range. The -D04594-GM code denotes a custom factory-programmed frequency plan generated by Skyworks ClockBuilder Pro, which removes the burden of in-system NVM programming.
Architecturally, the Si5345A uses a fractional-N MultiSynth divider per output, allowing non-integer frequency translations without compromising phase noise. The internal low-jitter VCO and digitally programmable loop bandwidth enable optimization for each application's jitter transfer characteristics. This makes the SI5345A well suited to reference clock generation for 100G/400G Ethernet PHYs, OTN/SONET/SDH line cards, FPGA transceiver reference chains, wireless base-station timing, and high-end broadcast video.
Typical applications include 100G/400G Ethernet switches, OTN/SONET/SDH line cards, FPGA/ASIC reference clock trees, wireless base-station timing boards, and broadcast video routers. The wide output format support and low jitter make it a flexible single-chip timing solution for mixed-signal boards that would otherwise require multiple oscillators or clock generators.
When designing with the SI5345A, place the 0.1 uF + 10 uF decoupling network as close as possible to each supply pin and expose the e-pad with at least 25 thermal vias to an internal ground pour. Use the ClockBuilder Pro configuration file attached to your -D04594 order code to load the pre-configured frequency plan into the IC; do not re-program the NVM unless intentionally overriding the factory image.
This page synthesizes verified distributor pricing, drop-in compatible alternatives, and practical PCB layout notes that are not aggregated on the manufacturer datasheet alone.
Alternativas drop-in para SI5345A-D04594-GMR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com SI5345A-D04594-GMR (mesmo formato e footprint) — diferindo em Package, Function, Output Frequency Range, Supply Voltage, Control Interface.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SI5345A-D04594-GM
✅ Drop-In✓ Em estoque
$25.9 / unidade
Ver ficha técnica →SI5345A-D-GMR
✅ Drop-In✓ Em estoque
$8.75 / unidade
Ver ficha técnica →SI5345A-D-GM
✅ Drop-In✓ Em estoque
$27.5 / unidade
Ver ficha técnica →SI5344B-D-GM
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$11.05 / unidade
Ver ficha técnica →SI5340A-D-GM
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$14.75 / unidade
Ver ficha técnica →SI5345A-D04594-GMR Especificações
| Product Type | Clock Synthesizer / Jitter Attenuator |
| Series | Si5345 (Si5345A family variant) |
| Número de saídas | 10 |
| Output Frequency Range | up to 1028 MHz (any frequency) |
| Output Logic Levels | LVDS, LVPECL, HCSL, CML, CMOS, HSTL, SSTL (selectable per output) |
| Supply Voltage (Core) | 1.71 V to 1.89 V |
| Control Interface | I2C |
| Faixa de temperatura de operação | -40 C to +85 C |
| Encapsulamento | QFN-64-EP (9x9 mm) with exposed thermal pad |
| Tipo de montagem | Surface Mount |
| Nível MSL | 2 (1 year floor life) |
| Status RoHS | Compliant |
| Factory Programming Code | D04594 (custom frequency plan via ClockBuilder Pro) |
| Packaging | Tape & Reel (TR) |
| Quantity per Reel | 1000 |
Configuração de pinos do SI5345A-D04594-GMR
| Pino 1 | IN0 — Reference clock input 0 (differential positive) |
| Pino 2 | IN0b — Reference clock input 0 (differential negative) |
| Pino 3 | VDD — Core supply 1.71 V to 1.89 V |
| Pino 4 | VDDA — Analog supply |
| Pino 5 | IN1 — Reference clock input 1 (differential positive) |
| Pino 6 | IN1b — Reference clock input 1 (differential negative) |
| Pino 7 | GND — Ground |
| Pino 8 | OUT0 — Clock output 0 (format programmable) |
| Pino 9 | OUT0b — Clock output 0 complementary |
| Pino 10 | VDDO — Output supply for bank 0 |
| Pino 11 | OUT1 — Clock output 1 |
| Pino 12 | OUT1b — Clock output 1 complementary |
| Pino 13 | GND — Ground |
| Pino 14 | OUT2 — Clock output 2 |
| Pino 15 | OUT2b — Clock output 2 complementary |
| Pino 16 | VDDO — Output supply for bank 1 |
| Pino 17 | OUT3 — Clock output 3 |
| Pino 18 | OUT3b — Clock output 3 complementary |
| Pino 19 | GND — Ground |
| Pino 20 | OUT4 — Clock output 4 |
| Pino 21 | OUT4b — Clock output 4 complementary |
| Pino 22 | VDDO — Output supply for bank 2 |
| Pino 23 | OUT5 — Clock output 5 |
| Pino 24 | OUT5b — Clock output 5 complementary |
| Pino 25 | GND — Ground |
| Pino 26 | OUT6 — Clock output 6 |
| Pino 27 | OUT6b — Clock output 6 complementary |
| Pino 28 | VDDO — Output supply for bank 3 |
| Pino 29 | OUT7 — Clock output 7 |
| Pino 30 | OUT7b — Clock output 7 complementary |
| Pino 31 | GND — Ground |
| Pino 32 | OUT8 — Clock output 8 |
| Pino 33 | OUT8b — Clock output 8 complementary |
| Pino 34 | VDDO — Output supply for bank 4 |
| Pino 35 | OUT9 — Clock output 9 |
| Pino 36 | OUT9b — Clock output 9 complementary |
| Pino 37 | GND — Ground |
| Pino 38 | SDA — I2C serial data |
| Pino 39 | SCL — I2C serial clock |
| Pino 40 | VDD — Core supply |
| Pino 41 | A0 — I2C address LSB |
| Pino 42 | GND — Ground |
| Pino 43 | nIRQ — Interrupt output (active low) |
| Pino 44 | nRST — Reset (active low) |
| Pino 45 | VDD — Core supply |
| Pino 46 | XO — Crystal oscillator driver output |
| Pino 47 | XI — Crystal oscillator input |
| Pino 48 | GND — Ground |
| Pino 49 | TEST — Test mode (tie to GND in normal operation) |
| Pino 50 | VDDA — Analog supply |
| Pino 51 | NC — Not connected |
| Pino 52 | NC — Not connected |
| Pino 53 | NC — Not connected |
| Pino 54 | NC — Not connected |
| Pino 55 | GND — Ground |
| Pino 56 | NC — Not connected |
| Pino 57 | NC — Not connected |
| Pino 58 | NC — Not connected |
| Pino 59 | VDD — Core supply |
| Pino 60 | NC — Not connected |
| Pino 61 | NC — Not connected |
| Pino 62 | NC — Not connected |
| Pino 63 | GND — Ground |
| Pino 64 | VDD — Core supply |
Aplicações típicas
SI5345A-D04594-GMR é adequado para 6 aplicaçãos: 100G/400G Ethernet Switch Timing, OTN/SONET/SDH Line Card Clocking, FPGA/ASIC Transceiver Reference Clock Tree, Wireless Base Station Timing, Broadcast Video Router Reference, Test & Measurement Instrumentation.
100G/400G Ethernet Switch Timing
The Si5345A-D04594-GMR's ten independently programmable outputs and sub-200 fs RMS jitter make it ideal as a single-chip reference tree for 100G/400G Ethernet switch ASICs. Each PHY typically needs a 156.25 MHz or 161.13 MHz reference, often in mixed LVDS and HCSL formats; the Si5345A can deliver up to ten of those references from one factory-programmed ClockBuilder Pro plan, eliminating multiple discrete oscillators. The QFN-64-EP package exposes a thermal pad that anchors the device to a ground pour for low-jitter ground-bounce performance.
Recomendado
OTN/SONET/SDH Line Card Clocking
OTN and SONET/SDH line cards require Stratum-3/3E-grade jitter performance on multiple reference outputs at 155.52 MHz, 311.04 MHz, and related multiples. The Si5345A-D04594-GMR delivers these frequencies with sub-200 fs RMS jitter while offering per-output format selection between LVDS and LVPECL to feed both legacy SONET framer ASICs and newer OTN mappers. Its I2C interface lets the host SoC change output enables and frequencies in-system during line-card bring-up.
Recomendado
FPGA/ASIC Transceiver Reference Clock Tree
Modern FPGAs and ASICs with multi-gigabit transceivers need multiple low-jitter reference clocks at 100 MHz, 122.88 MHz, 156.25 MHz, and other rates. The Si5345A-D04594-GMR's ten-output architecture allows one device to feed an entire transceiver bank, and the per-pin LVDS/LVPECL/HCSL output selection matches the input requirements of Xilinx, Intel (Altera), and Microchip FPGA transceivers. The factory -D04594 plan removes in-system NVM programming overhead during prototyping.
Recomendado
Wireless Base Station Timing
4G/5G base-station RRUs and BBUs require multiple sample-rate clocks (e.g., 122.88 MHz, 153.6 MHz, 245.76 MHz) with extremely low jitter to support high-order QAM modulation. The Si5345A-D04594-GMR's sub-200 fs RMS jitter and any-frequency flexibility let one IC serve the entire timing tree of a small-cell or macro base-station card. Its -40 C to +85 C industrial temperature range covers outdoor radio unit deployments.
Recomendado
Broadcast Video Router Reference
Broadcast video routers (SMPTE 424M, 425M, 2082) require ultra-low-jitter 148.35 MHz and 148.5 MHz references for SDI serializers and deserializers. The Si5345A-D04594-GMR provides these frequencies with any-format output selection, allowing direct drive of SDI cable drivers without external level translation. The factory -D04594 frequency plan guarantees deterministic frequencies at first power-up, which is critical for broadcast hardware that must boot into a known state.
Recomendado
Test & Measurement Instrumentation
High-end oscilloscopes, BERTs, and signal analyzers demand multiple clean reference clocks across the chassis. The Si5345A-D04594-GMR's factory programming removes the risk of in-system configuration failure and provides a deterministic, repeatable clocking scheme for production test instruments. Its low RMS jitter improves instrument phase-noise floor, which directly translates to better measurement accuracy at high modulation frequencies.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SI5345A-D04594-GMR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SI5345A-D04594-GM | SI5345A-D-GMR | SI5345A-D-GM | SI5344B-D-GM | SI5340A-D-GM |
|---|---|---|---|---|---|---|
| Package | QFN-64-EP (9x9 mm) | QFN-64-EP (9x9 mm) - same | QFN-64-EP (9x9 mm) - same | QFN-64-EP (9x9 mm) - same | QFN-44 - DIFFERENT (smaller) | QFN-44 - DIFFERENT (smaller) |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Number of Outputs | 10 | 10 | 10 | 10 | 4 (-60%) | 4 (-60%) |
| Max Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz |
| Factory Programming | Yes (-D04594) | Yes (-D04594) | No (unprogrammed) | No (unprogrammed) | No | No |
| RMS Jitter | < 200 fs | < 200 fs | < 200 fs | < 200 fs | < 200 fs | < 300 fs |
| Control Interface | I2C | I2C | I2C | I2C | I2C | I2C/SPI |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Principais diferenciais
- Factory-programmed frequency plan eliminates in-system NVM programming risk (vs SI5345A-D-GMR)
- 10 outputs vs 4 in lower-count variants (vs SI5344B-D-GM)
- Per-pin format selection (LVDS/LVPECL/HCSL/CML/CMOS/HSTL/SSTL) (vs SI5340A-D-GM)
Notas de projeto
Per the Skyworks Si5345 datasheet, place a 0.1 uF X7R ceramic capacitor as close as possible (within 2 mm) to each VDD, VDDA, and VDDO pin, paired with a 10 uF bulk capacitor on each supply rail. The exposed thermal pad must be soldered to a continuous ground pour stitched with at least 25 thermal vias (0.3 mm drill, 0.6 mm pitch) to provide both electrical reference and a low-impedance thermal path. Keep clock output traces 50 ohm differential (100 ohm differential) with length matching within 5 mils across each pair.
Route the crystal traces (XI, XO) as short and symmetric as possible, surrounded by a ground guard trace on both sides to keep stray capacitance below 5 pF. Use a fundamental-mode crystal with ESR < 50 ohms and load capacitance specified by ClockBuilder Pro for the -D04594 plan. If the application is noise-sensitive, isolate the analog VDD/VDDA pins from the digital VDD with a ferrite bead to prevent digital switching noise from coupling into the PLL loop.
The -D04594 factory programming is loaded at production; do NOT issue an in-system NVM reprogramming command unless intentionally overriding the factory image, because the resulting clock tree may not match the order code on the reel label. The I2C address is set by the A0 pin (typically 0x6E or 0x6F); verify against the ClockBuilder Pro header file before polling. Outputs that are disabled at the Si5345A still draw leakage current - tie unused complementary outputs (OUTxb) to GND through 50 ohm if not used.
Informações de conformidade
RoHS compliant per JLCPCB, Mouser, and DigiKey listings. Not AEC-Q100 qualified - this part targets industrial/commercial, not automotive. Halogen-free and lead-free per Skyworks product family standards.
