SI5391A-A-GM - 12-Output Ultra-Low-Jitter Clock Generator | Skyworks
N.º da peça: SI5391A-A-GM ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $47.63 | $47,63 |
| 10 | $43.85 | $438,50 |
| 100 | $38.92 | $3.892,00 |
| 500 | $34.78 | $17.390,00 |
| 1.000 | $31.05 | $31.050,00 |
SI5391A-A-GM Visão geral
A clock generator is a timing IC that derives one or more synchronized output frequencies from a single reference and distributes them as low-jitter CMOS, HCSL, LVDS, or LVPECL clocks to system sub-blocks. Clock generators sit in the broader timing hierarchy: oscillator -> PLL -> clock synthesizer -> clock generator -> clock buffer/jitter cleaner. The SI5391A-A-GM occupies the high-performance end of the clock-generator taxonomy, merging low-jitter PLL jitter-cleaning with MultiSynth fractional synthesis - it functions simultaneously as a synthesizer and a jitter-cleaner.
Key specifications include 95 fs RMS typical phase jitter (12 kHz-20 MHz), 1.5 ps peak-to-peak period jitter, four differential reference inputs (XTAL, CMOS, LVDS, HCSL, LVPECL), twelve configurable output drivers, integrated LDO regulators, and I2C/SPI host control. Loss-of-lock and loss-of-reference detection support broadcast video, OTN, and SONET/SDH holdover transitions.
The architecture pairs a high-Q analog MultiSynth VCO with four fractional-output MultiSynth blocks, allowing independent, non-coupled output frequencies up to 1028 MHz. Each output driver independently supports CMOS, HCSL, LVDS, and LVPECL standards through register configuration, eliminating external level-translation components.
Typical applications include 100G/400G optical-module line-card clock trees, broadcast video reference clock fan-out, wireless baseband timing, OTN/SONET/SDH line cards, FPGA and ASIC reference-clock distribution in test & measurement ATE, and server/storage PCIe Gen 5 reference-clock generation.
When designing with the SI5391A-A-GM, use Skyworks ClockBuilder Pro to generate the personalized configuration script because each shipping variant is factory pre-programmed with a unique NVM image. Plan PCB layout to keep the 64-VFQFN exposed pad soldered to a continuous low-thermal-resistance ground plane.
This page synthesizes authoritative datasheet specs, current distributor pricing as of 2026-10-10, drop-in same-package alternatives, and AEO-oriented engineering content not found in the Si5391 datasheet alone.
Alternativas drop-in para SI5391A-A-GM — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SI5391B-A-GM
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5391C-A-GM
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5391D-A-GM
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5391A-A13791-GM
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5391A-A17776-GM
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SI5391A-A-GM Especificações
| Número de saídas | 12 |
| Maximum Output Frequency | 1028 MHz |
| Phase Jitter (12 kHz-20 MHz) | 95 fs RMS typical |
| Reference Inputs | 4 (XTAL, CMOS, LVDS, HCSL, LVPECL compatible) |
| Synthesis Modes | Integer and Fractional (MultiSynth) |
| Output Logic Standards | CMOS, HCSL, LVDS, LVPECL (per-pin configurable) |
| Core Supply Voltage | 1.8 V |
| I/O Supply Voltage | 3.3 V |
| On-Chip VCO | Yes (MultiSynth) |
| Loss-of-Lock Detection | Yes |
| Loss-of-Signal Detection | Yes |
| Host Interface | I2C / SPI |
| Encapsulamento | 64-VFQFN Exposed Pad (10 x 10 mm) |
| Faixa de temperatura de operação | -40 C to +85 C (industrial grade -GM suffix) |
| Status RoHS | Compliant |
Configuração de pinos do SI5391A-A-GM
| Pino 1 | IN0_P — Reference input 0, positive |
| Pino 2 | IN0_N — Reference input 0, negative |
| Pino 3 | VDD — 1.8 V core supply |
| Pino 4 | GND — Ground (signal) |
| Pino 5 | IN1_P — Reference input 1, positive |
| Pino 6 | IN1_N — Reference input 1, negative |
| Pino 7 | VDD33 — 3.3 V I/O supply |
| Pino 8 | XIN — Crystal oscillator input |
| Pino 9 | XOUT — Crystal oscillator output |
| Pino 10 | VDD — 1.8 V core supply |
| Pino 11 | IN2_P — Reference input 2, positive |
| Pino 12 | IN2_N — Reference input 2, negative |
| Pino 13 | GND — Ground (signal) |
| Pino 14 | OUT0 — Clock output 0 |
| Pino 15 | OUT0B — Complementary clock output 0 |
| Pino 16 | VDDO — Output driver supply |
| Pino 17 | OUT1 — Clock output 1 |
| Pino 18 | OUT1B — Complementary clock output 1 |
| Pino 19 | GND — Ground (signal) |
| Pino 20 | OUT2 — Clock output 2 |
| Pino 21 | OUT2B — Complementary clock output 2 |
| Pino 22 | VDDO — Output driver supply |
| Pino 23 | OUT3 — Clock output 3 |
| Pino 24 | OUT3B — Complementary clock output 3 |
| Pino 25 | GND — Ground (signal) |
| Pino 26 | OUT4 — Clock output 4 |
| Pino 27 | OUT4B — Complementary clock output 4 |
| Pino 28 | VDDO — Output driver supply |
| Pino 29 | OUT5 — Clock output 5 |
| Pino 30 | OUT5B — Complementary clock output 5 |
| Pino 31 | GND — Ground (signal) |
| Pino 32 | OUT6 — Clock output 6 |
| Pino 33 | OUT6B — Complementary clock output 6 |
| Pino 34 | VDDO — Output driver supply |
| Pino 35 | OUT7 — Clock output 7 |
| Pino 36 | OUT7B — Complementary clock output 7 |
| Pino 37 | GND — Ground (signal) |
| Pino 38 | OUT8 — Clock output 8 |
| Pino 39 | OUT8B — Complementary clock output 8 |
| Pino 40 | VDDO — Output driver supply |
| Pino 41 | OUT9 — Clock output 9 |
| Pino 42 | OUT9B — Complementary clock output 9 |
| Pino 43 | GND — Ground (signal) |
| Pino 44 | OUT10 — Clock output 10 |
| Pino 45 | OUT10B — Complementary clock output 10 |
| Pino 46 | VDDO — Output driver supply |
| Pino 47 | OUT11 — Clock output 11 |
| Pino 48 | OUT11B — Complementary clock output 11 |
| Pino 49 | GND — Ground (signal) |
| Pino 50 | IN3_P — Reference input 3, positive |
| Pino 51 | IN3_N — Reference input 3, negative |
| Pino 52 | VDD — 1.8 V core supply |
| Pino 53 | SDA — I2C serial data |
| Pino 54 | SCL — I2C serial clock |
| Pino 55 | CS — SPI chip select |
| Pino 56 | SCLK — SPI clock |
| Pino 57 | SDIO — SPI data |
| Pino 58 | INT — Interrupt output (open-drain) |
| Pino 59 | RST — Device reset (active-low) |
| Pino 60 | STATUS — Loss-of-lock / loss-of-signal indicator |
| Pino 61 | NC — Not connected (per datasheet) |
| Pino 62 | NC — Not connected (per datasheet) |
| Pino 63 | NC — Not connected (per datasheet) |
| Pino 64 | NC — Not connected (per datasheet) |
Aplicações típicas
SI5391A-A-GM é adequado para 8 aplicaçãos: 100G/400G Optical Module Timing, Broadcast Video Reference Clock Fan-Out, Wireless Baseband Reference Clock, OTN/SONET/SDH Line Card Timing, FPGA/ASIC Reference Clock Distribution, Automated Test Equipment (ATE) Timing, Server / Storage PCIe Clock Generation, Test & Measurement Instrumentation.
100G/400G Optical Module Timing
The SI5391A-A-GM provides reference clocks for coherent optics in 100G and 400G transceiver modules. With 95 fs RMS phase jitter and 1028 MHz maximum output frequency, it directly drives DSP and serializer blocks meeting IEEE 802.3ba/bj jitter masks. The device generates multiple unrelated frequencies from a single reference, eliminating multiple discrete oscillators in QSFP-DD and OSFP module designs. Its 1.8 V core supply fits modern DSP power budgets, while 3.3 V I/O tolerant pins interface with legacy FPGA SerDes.
Recomendado
Broadcast Video Reference Clock Fan-Out
The SI5391A-A-GM is used in broadcast video routers, switchers, and SDI infrastructure where multiple video format clocks must be distributed. Its twelve outputs independently support CMOS and LVPECL levels required for SDI serializers. With on-chip loss-of-lock and loss-of-reference detection, the device enables seamless backup-reference switching across SMPTE 424M and 292M standards. The integer/fractional MultiSynth synthesis guarantees any-format compatibility without requiring multiple oscillators.
Recomendado
Wireless Baseband Reference Clock
For 4G/5G baseband digital front-end cards and remote-radio-head (RRH) units, the SI5391A-A-GM delivers low-jitter reference clocks to ADC/DAC chains and FPGA transceivers. Its 95 fs RMS jitter performance ensures phase-noise compliance for LTE and 5G NR radios, while the 12-output capacity drives multiple data converters with unrelated sampling rates. The 64-VFQFN exposed-pad package supports the -40 C to +85 C industrial temperature range required for outdoor radio units.
Recomendado
OTN/SONET/SDH Line Card Timing
The SI5391A-A-GM serves as the central clock generator in OTN, SONET, and SDH multiplexer line cards. Its ability to produce multiple independent clock frequencies from a single Stratum-3 reference simplifies line card architecture. Loss-of-lock and loss-of-signal detection support automatic switchover to backup references, while on-chip LDO regulators reduce external component count in space-constrained line-card designs. Jitter generation stays within Telcordia GR-253-CORE masks.
Recomendado
FPGA/ASIC Reference Clock Distribution
In high-density FPGA and ASIC designs, the SI5391A-A-GM provides up to 12 independent clock domains from a single reference, supporting diverse fabric, transceiver, and memory-controller requirements. Its configurable CMOS/LVDS/HCSL/LVPECL output drivers eliminate external level translators. I2C and SPI control interfaces integrate seamlessly into standard SoC firmware drivers. MultiSynth fractional division supports non-integer relationships between input and output clocks.
Recomendado
Automated Test Equipment (ATE) Timing
In automated test equipment for semiconductors and high-speed serial interfaces, the SI5391A-A-GM delivers deterministic, factory-programmed clock trees to instrument channels. Its NVM-programmable configuration ensures identical timing across all ATE pin-electronics boards, simplifying calibration. 95 fs RMS jitter supports accurate measurement of PCIe, USB, and SerDes jitter tolerance. Twelve outputs per IC drive multi-channel parallel test structures.
Recomendado
Server / Storage PCIe Clock Generation
For data center server and NVMe storage subsystems, the SI5391A-A-GM supplies reference clocks to PCIe Gen 4/5 endpoints and SoC tiles. Its low 95 fs RMS phase jitter supports PCIe Gen 5 common-clock architectures across multiple slots, while per-pin LVDS/HCSL output flexibility drives CML retimer chains directly. Industrial-grade -GM temperature rating suits ambient server airflow conditions and 24/7 operating duty cycles.
Recomendado
Test & Measurement Instrumentation
The SI5391A-A-GM delivers low-jitter multi-frequency clocks to oscilloscope, spectrum analyzer, and signal-generator subsystems requiring factory-calibrated precision. Custom NVM programming enables each instrument's specific frequency plan, simplifying firmware and eliminating per-unit oscillator trimming. Twelve outputs feed ADC, DAC, and front-end mixer blocks simultaneously, while the on-chip PLL holdover preserves output phase between reference reselects.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SI5391A-A-GM — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SI5391B-A-GM | SI5391C-A-GM | SI5391D-A-GM |
|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 64-VFQFN Exposed Pad | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same |
| Number of Outputs | 12 | 12 | 12 | 12 |
| Maximum Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz | 350 MHz |
| Reference Inputs | 4 | 4 | 4 | 4 |
| Output Logic Standards | CMOS / HCSL / LVDS / LVPECL (per-pin) | Same family capability | Same family capability | Same family capability |
| NVM Programmable | Yes (factory-programmed) | Yes (factory-programmed) | Yes (factory-programmed) | Yes (factory-programmed) |
Principais diferenciais
- Highest output count in Si539x family (vs SI5391D-A-GM)
- Best-in-class sub-100fs RMS phase jitter (vs Generic PLL clock generators)
- On-chip NVM with per-shipment programming (vs Generic blank-clock devices)
Notas de projeto
Solder the SI5391A-A-GM's exposed thermal pad to a continuous low-impedance ground island occupying at least 50% of the package underside area, with at least 6 thermal via stitching into an inner ground plane. The 64-VFQFN package's power dissipation under 1 GHz full-output loading can rise above 1 W; insufficient ground-plane area causes junction-temperature derating above 85 C ambient.
Route the four differential reference inputs (IN0_P/N, IN1_P/N, IN2_P/N, IN3_P/N) as length-matched 100-ohm differential pairs from the SI5391A pins to the connector or oscillator source. Keep the XIN/XOUT traces short and surrounded by ground pour - a too-long or noisy crystal trace pulls the MultiSynth VCO phase noise and degrades the 95 fs RMS jitter spec.
Use the Skyworks ClockBuilder Pro tool (free download) to generate the NVM register map for each SI5391A-Axxxxx-GM variant; ad-hoc register scripts frequently mis-configure integer/fractional synthesis mode and result in un-intended output frequencies or failure to lock. Each customer receives a unique NVM image, so a script authored for one -Axxxxx-GM variant will not work on another.
Bypass each VDD/VDD33 pin with a 0.1 uF ceramic capacitor placed within 2 mm of the pin. Add a 4.7 uF bulk capacitor near the package entry point on the 1.8 V rail. The SI5391A-A-GM's integrated LDO regulators provide clean internal supplies, but noisy external rails can couple into MultiSynth fractional dividers and increase jitter by 15-25 fs.
Informações de conformidade
RoHS compliant per Skyworks product page; -GM suffix indicates industrial-grade -40 C to +85 C; -AEC-Q100 variants are not part of this product family. Conflict minerals compliance follows Skyworks' standard declaration. Source: https://www.skyworksinc.com/en/products/timing/ultra-low-jitter-clock-generators/si5391a.
