SN74HC86N - Quad 2-Input XOR Gate, 14-PDIP | Texas Instruments
N.º da peça: SN74HC86N ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $0.59 | $0,59 |
| 10 | $0.51 | $5,10 |
| 100 | $0.36 | $36,00 |
| 500 | $0.28 | $140,00 |
| 1.000 | $0.22 | $220,00 |
SN74HC86N Visão geral
An XOR gate is a fundamental combinational logic primitive that outputs a HIGH whenever its two inputs differ. In digital system hierarchies, XOR gates sit alongside AND, OR, and NOT gates as building blocks of arithmetic logic units, parity generators, comparators, and crypto primitives. The 74HC86 places four such gates in one package, reducing board area and interconnect length for glue logic.
Key features of the SN74HC86N include ±5.2 mA output drive, wide 2 V to 6 V supply range, low input current of ±1 µA, typical propagation delay around 13 ns at 5 V/15 pF, and ±20 µA quiescent supply current. Its CMOS outputs produce rail-to-rail logic swings, simplifying interfacing with downstream CMOS loads. The HC family is pin-compatible with the LS TTL legacy while consuming a fraction of the power.
Architecturally, the SN74HC86 uses a CMOS NAND/NOR-equivalent XOR topology realized with complementary pull-up and pull-down networks. The high-speed CMOS process delivers sub-15 ns gate delay at 5 V while keeping static dissipation negligible. Inputs are CMOS with Schmitt-trigger-like hysteresis improving noise immunity in noisy industrial environments.
Typical applications include parity generation and checking in memory and communication systems, half-adder and full-adder construction, controlled inverters, programmable logic replacement, and signal conditioning for comparators. Designers also use XOR gates for phase detectors in PLLs, simple encryption/decryption stages, and switch-debounce or edge-detection circuits.
When designing with the SN74HC86N, observe standard CMOS handling rules: tie unused inputs to VCC or GND through a resistor to prevent floating inputs that draw shoot-through current. The 14-PDIP package is suitable for breadboards, prototypes, and legacy through-hole assemblies where surface-mount land patterns are not desired.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a decision-ready snapshot of the SN74HC86N.
Alternativas drop-in para SN74HC86N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com SN74HC86N (mesmo formato e footprint) — diferindo em Logic Family, Output Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SN74HCT86N
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
CD74HC86E
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SN74HC86DR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
MM74HC86N
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
74HC86N,652
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SN74HC86N Classificações máximas e características elétricas
| Logic Type | XOR (Exclusive OR) |
| Number of Channels | 4 |
| Number of Inputs per Gate | 2 |
| Logic Family | 74HC (High-Speed CMOS) |
| Supply Voltage (VCC) | 2 V to 6 V |
| Output Drive Strength | ±5.2 mA |
| Quiescent Current (ICC) | 20 µA maximum |
| Input Current | ±1 µA maximum |
| Tipo de saída | CMOS (push-pull) |
| Temperatura de operação | -40 °C to +85 °C |
| Encapsulamento | 14-PDIP (N), through-hole, 7.62 mm (0.300 in) |
| Tipo de montagem | Through-Hole |
| Nível MSL | Not Applicable (through-hole) |
| Boolean Function | Y = A ⊕ B |
| Input Threshold | CMOS-compatible |
Configuração de pinos do SN74HC86N
| Pino 1 | 1A — Gate 1 input A |
| Pino 2 | 1B — Gate 1 input B |
| Pino 3 | 1Y — Gate 1 output Y = A XOR B |
| Pino 4 | 2A — Gate 2 input A |
| Pino 5 | 2B — Gate 2 input B |
| Pino 6 | 2Y — Gate 2 output Y = A XOR B |
| Pino 7 | GND — Ground (0 V) |
| Pino 8 | 3Y — Gate 3 output Y = A XOR B |
| Pino 9 | 3A — Gate 3 input A |
| Pino 10 | 3B — Gate 3 input B |
| Pino 11 | 4Y — Gate 4 output Y = A XOR B |
| Pino 12 | 4A — Gate 4 input A |
| Pino 13 | 4B — Gate 4 input B |
| Pino 14 | VCC — Positive supply voltage (2 V to 6 V) |
Aplicações típicas
SN74HC86N é adequado para 6 aplicaçãos: Parity Generator and Checker, Half-Adder and Full-Adder Construction, Phase Detector in PLL Circuits, Controlled Inverter (Programmable Logic), Comparator and Equality Detector, Switch Debounce and Edge Detection.
Parity Generator and Checker
The SN74HC86N's four XOR gates make it ideal for parity generation and checking in memory and serial communication systems. In an 8-bit parity checker, two SN74HC86N gates can XOR all eight data bits; the cascaded XOR topology produces a single-bit parity output in a single 14-PDIP package. The 2-6V VCC range and ±5.2 mA drive support direct CMOS interfacing, while the low 20 µA quiescent current suits battery-backed memory systems. Designers use this gate to detect single-bit errors in DRAM buses, UART frames, and RAID storage paths where deterministic parity is required.
Recomendado
Half-Adder and Full-Adder Construction
The SN74HC86N can build a 1-bit half-adder in a single package: one XOR gate produces the sum bit, and one AND gate (from a separate 74HC08N) produces the carry. For a full adder, two XOR gates plus two additional gates form sum and carry-out logic. According to TI datasheets, the SN74HC86N's CMOS outputs drive the cascaded adder stages without buffering. Operating at 5 V, the typical 13 ns propagation delay keeps ripple-carry adders fast enough for many control loops, while the 14-PDIP package suits educational and prototype adder boards.
Recomendado
Phase Detector in PLL Circuits
An XOR gate is the textbook phase detector for analog phase-locked loops. The SN74HC86N provides four independent XOR phase detectors on one die, useful for multi-loop or quadrature PLL designs. The 2-6V VCC range matches typical PLL charge-pump supply rails. According to the TI datasheet, the symmetric output drive and short propagation delay produce a clean phase-error voltage when the XOR output is filtered by an RC network. Designers use this configuration in clock recovery, FSK demodulation, and motor control loops.
Recomendado
Controlled Inverter (Programmable Logic)
When one input of an XOR gate is tied to a control signal, the gate becomes a controlled inverter: the output equals the input when control is LOW, and equals the inverted input when control is HIGH. The SN74HC86N provides four such controlled inverters, useful for programmable logic replacement, sign-magnitude to two's-complement conversion, and digital signal inversion in audio and video paths. The 5.2 mA output drive lets each output feed a small bus segment, and the CMOS input thresholds ensure clean switching with microcontroller GPIO signals at 3.3 V or 5 V.
Recomendado
Comparator and Equality Detector
A multi-bit equality detector cascades XOR gates to compare two words bit by bit, then ORs the results. Two SN74HC86N packages can compare two 8-bit words and produce a single equality flag. According to TI datasheets, the SN74HC86N's CMOS outputs produce a valid equality flag within a few gate delays, suitable for address-matching in memory decoding and instruction validation in simple microcontrollers. The 14-PDIP through-hole package makes this a popular choice in educational kits and breadboard prototypes.
Recomendado
Switch Debounce and Edge Detection
The SN74HC86N's XOR gate can build a switch debounce circuit when combined with an RC network: a single XOR gate detects transitions between two delayed versions of the switch signal, producing a clean edge output free of contact bounce. The 2-6V VCC range lets the gate operate directly from battery or regulated logic rails. Designers also use the XOR as a simple edge detector for digital tachometers and event counters. The 14-PDIP package suits hand-wired hobby and lab prototypes where surface-mount is impractical.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SN74HC86N — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SN74HCT86N | CD74HC86E | MM74HC86N | 74HC86N,652 |
|---|---|---|---|---|---|
| Package | 14-PDIP (N) | 14-PDIP (N) - same | 14-PDIP (N) - same | 14-PDIP (N) - same | 14-PDIP (N) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | onsemi | Nexperia |
| Supply Voltage (VCC) | 2 V to 6 V | 4.5 V to 5.5 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V |
| Output Drive | ±5.2 mA | ±5.2 mA | ±5.2 mA | ±5.2 mA | ±5.2 mA |
| Input Threshold | CMOS | TTL-compatible | CMOS | CMOS | CMOS |
| Logic Function | Y = A XOR B | Y = A XOR B | Y = A XOR B | Y = A XOR B | Y = A XOR B |
| Number of Gates | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +125 °C |
Principais diferenciais
- TTL-compatible input threshold option in same package (vs SN74HCT86N)
- Cross-brand availability from onsemi and Nexperia (vs MM74HC86N (onsemi))
- Through-hole PDIP form factor for legacy and educational use (vs SN74HC86DR (SOIC-14))
Notas de projeto
Always tie unused XOR gate inputs to VCC or GND through a pull resistor (typically 10 kΩ). A floating CMOS input on the SN74HC86N can drift to mid-rail and cause the output stage to conduct shoot-through current, raising quiescent current from the 20 µA spec to several milliamps and potentially damaging the device over time. This is a standard CMOS handling rule that applies to all 74HC family parts.
Estimated: at 5 V VCC and 1 MHz switching, the SN74HC86N typically draws ICC around 0.5 mA to 2 mA depending on load capacitance. Place a 0.1 µF decoupling capacitor as close as practical to the VCC pin (pin 14) to suppress switching transients. The CMOS outputs source and sink 5.2 mA per pin, so total package dissipation must stay within the PDIP thermal envelope at high duty cycles.
When using the SN74HC86N to drive long PCB traces or cables, add a 33 Ω to 100 Ω series resistor near the output to limit ringing. The 5.2 mA output drive is modest, so capacitive loads above 50 pF may cause significant edge ringing. For mixed 3.3 V/5 V systems, prefer the SN74HCT86N variant to ensure TTL-compatible logic thresholds when driven from 5 V CMOS sources.
Informações de conformidade
RoHS, REACH, lead-free, and halogen-free status for SN74HC86N (14-PDIP) not explicitly stated in the provided verified web data. The 14-PDIP variant typically contains lead in the through-hole plating; for lead-free, prefer the SN74HC86DR (SOIC-14) or SN74HC86PW (TSSOP-14) suffixes.
