SN74HC86NE4 - Quad 2-Input XOR Gate, 14-PDIP | Texas Instruments
N.º da peça: SN74HC86NE4 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $0.49 | $0,49 |
| 10 | $0.41 | $4,10 |
| 100 | $0.32 | $32,00 |
| 500 | $0.24 | $120,00 |
| 1.000 | $0.18 | $180,00 |
SN74HC86NE4 Visão geral
What is an XOR gate? An XOR (Exclusive-OR) gate is a fundamental two-input digital logic primitive whose output is HIGH only when the two inputs differ. Positioned within the broader gates-and-inverters IC category, XOR gates sit alongside AND, OR, NAND, NOR, and INVERTER cells, and are widely deployed in parity generators, comparators, half adders, controlled inverters, and arithmetic logic units. A single HC86 device packs four independent XOR gates into one 14-pin package, saving board area and reducing part count versus discrete implementations.
Key features include balanced CMOS outputs, low input current of ±1 µA maximum, significant power-reduction versus LSTTL equivalents, and an operating temperature range of -40 °C to +85 °C suitable for industrial applications. The HC family also provides high noise immunity (typically 30% of V_CC as the noise margin) and supports fan-out to 10 LSTTL loads, simplifying interface to legacy bipolar logic without level shifters. Clamp diodes on the inputs allow voltages up to 1.5 V above V_CC without damage.
Architecturally, the SN74HC86NE4 uses a silicon-gate CMOS process to deliver HCMOS-equivalent speed at one-fifth the static power of LSTTL. Its TTL-compatible input thresholds (V_IL ≈ 0.9 V at 5 V, V_IH ≈ 3.15 V) allow direct interfacing with legacy bipolar logic without external pull-ups. The four gates are partitioned symmetrically as 1A/1Y, 2A/2Y, 3A/3Y, 4A/4Y to ease PCB routing, and an internal thermal-shutdown feature is absent (CMOS logic is inherently current-limited by design).
Typical applications include parity generation and checking in data communication busses, half and full adder construction for low-bit arithmetic, true/complement control logic for op-amp switching, phase-detector networks in PLL synthesizers, and address decoders in memory systems. Designers also use the HC86 for binary-to-Gray code conversion, which is essential in optical encoders and shaft position decoding.
When designing with this part, ensure unused inputs are tied to V_CC or GND through 1 kΩ pull-down/up resistors rather than left floating to prevent excess current and propagation of noise through the CMOS input stages. Operating above 6 V will damage the device; operating below 2 V disables the internal logic thresholds and produces undefined outputs.
This page synthesizes current distributor pricing, AEO-optimized FAQ entries, verified drop-in alternatives, and practical design notes that extend the manufacturer datasheet with engineering-grade decision support.
Alternativas drop-in para SN74HC86NE4 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com SN74HC86NE4 (mesmo formato e footprint) — diferindo em Logic Family, Output Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
SN74HC86N
✅ Drop-In✓ Em estoque
$0.22 / unidade
Ver ficha técnica →SN74HC86NE4-ND
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
MC74HC86ANG
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
MC74HC86AN
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
CD4070BE
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
CD4030BE
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
SN74HC86NE4 Classificações máximas e características elétricas
| Logic Family | HC (High-Speed CMOS) |
| Logic Function | Quadruple 2-Input XOR (Exclusive-OR) Gate |
| Number of Gates | 4 |
| Number of Inputs per Gate | 2 |
| Number of Channels | 4 |
| Tipo de saída | Single-Ended, Push-Pull CMOS |
| Operating Voltage Range (VCC) | 2 V to 6 V |
| Maximum Drive Strength | 5.2 mA |
| Input Leakage Current | ±1 µA (max) at 6 V |
| Propagation Delay (tpd) | 26 ns (typ at 2 V), 13 ns (typ at 4.5 V), 10 ns (typ at 6 V), 6 ns (typ at 5 V C_L = 50 pF) |
| Temperatura de operação | -40 °C to +85 °C |
| Output Drive (LSTTL fan-out) | 10 LSTTL loads |
| Encapsulamento / Caixa | 14-PDIP (N) 7.6 mm body width |
| Tipo de montagem | Through-Hole |
| Input Clamp Diode Tolerance | 1.5 V above VCC |
| Status RoHS | Compliant (Pb-free NE4 suffix) |
| Lead-Free Finish | Yes (NiPdAu) |
Configuração de pinos do SN74HC86NE4
| Pino 1 | 1A — Gate 1 input A |
| Pino 2 | 1B — Gate 1 input B |
| Pino 3 | 1Y — Gate 1 output Y = A XOR B |
| Pino 4 | 2A — Gate 2 input A |
| Pino 5 | 2B — Gate 2 input B |
| Pino 6 | 2Y — Gate 2 output Y = A XOR B |
| Pino 7 | GND — Ground (0 V) |
| Pino 8 | 3Y — Gate 3 output Y = A XOR B |
| Pino 9 | 3A — Gate 3 input A |
| Pino 10 | 3B — Gate 3 input B |
| Pino 11 | 4Y — Gate 4 output Y = A XOR B |
| Pino 12 | 4A — Gate 4 input A |
| Pino 13 | 4B — Gate 4 input B |
| Pino 14 | VCC — Positive supply voltage (2 V to 6 V) |
Aplicações típicas
SN74HC86NE4 é adequado para 7 aplicaçãos: Parity Generator/Checker, Half and Full Adder Construction, Binary-to-Gray Code Converter, True/Complement Control Logic, Phase Detector / Phase-Frequency Detector, Address Decoder / Memory Bank Select, Comparator / Equality Detector.
Parity Generator/Checker
Parity generation and checking across data buses and communication channels is a classic SN74HC86NE4 application. Each of the four XOR gates cascades to XOR multiple data bits together so the sum modulo 2 of the inputs appears at the output - the fundamental parity function. With 6 ns propagation delay at 5 V and TTL-compatible inputs, the SN74HC86NE4 can drive the parity tree for byte-wide (8-bit) data at clock rates to ~50 MHz, covering most serial and parallel data busses. Compared with a discrete-transistor parity tree the SN74HC86NE4 saves board area, reduces fanout loading on upstream drivers, and consumes far less quiescent current than the equivalent 74LS86 implementation. Engineers commonly pair the SN74HC86NE4 with a parity error flag D flip-flop to implement full transmit/receive parity checking for UARTs and memory interfaces.
Recomendado
Half and Full Adder Construction
A half adder consists of one XOR gate for the SUM output and one AND gate for the CARRY output. Two gates of the SN74HC86NE4 plus an external AND gate provide a complete half adder cell, and cascading four HC86-based half adders with carry-lookahead gates implements a full 1-bit adder slice used in ALU prototyping and educational hardware. The SN74HC86NE4's CMOS outputs drive 10 LSTTL loads, making it suitable for fanout into downstream logic without intermediate buffers. The wide 2-6 V operating range also supports low-voltage adder designs operating at 3.3 V core logic with TTL-compatibility to upstream 5 V microcontroller GPIO pins where required.
Recomendado
Binary-to-Gray Code Converter
Binary-to-Gray code conversion is implemented naturally with XOR gates - each Gray bit equals the binary bit XORed with the next higher-order binary bit. Cascading four SN74HC86NE4 XOR gates produces a 4-bit Gray code encoder in a single 14-PDIP device, while extending the technique to 8 bits requires only two SN74HC86NE4 packages. Gray code minimizes bit-transition errors in shaft encoders, optical position sensors, and Karnaugh map addressing applications. The SN74HC86NE4's 6 ns propagation delay at 5 V makes it suitable for high-speed encoder chains where miscounts from bit-skew must be avoided across rapid input code transitions.
Recomendado
True/Complement Control Logic
When one input of an XOR gate is held LOW the output follows the other input directly; when that control input is held HIGH the output inverts. This true/complement property makes the SN74HC86NE4 ideal as a polarity-switching element in op-amp gain-configurable circuits, instrumentation multiplexers, and protocol-selectable interface logic. Driving each gate's control pin from a DIP switch or microcontroller GPIO enables software-programmable signal inversion without changing analog front-end hardware. The SN74HC86NE4's symmetric CMOS output stage and 5.2 mA drive make it a robust interface between low-power control logic and downstream analog switches or relay drivers.
Recomendado
Phase Detector / Phase-Frequency Detector
XOR gates serve as simple phase detectors in PLL synthesizer designs where both reference and feedback signals are square waves at 50% duty cycle. The averaged output of one SN74HC86NE4 gate is a triangular waveform whose DC offset is proportional to the phase difference between inputs - a classic type-I phase detector for cost-sensitive PLLs used in audio synthesizers and motor speed controls. When the two inputs are in phase the XOR output is constantly LOW; when out of phase by 90° the output is a 50%-duty square wave whose average is VCC/2. The SN74HC86NE4's CMOS outputs cleanly drive an external op-amp loop filter stage, and its 5 V operating tolerance matches typical PLL loop filter supply rails.
Recomendado
Address Decoder / Memory Bank Select
Address decoding in memory-mapped microcontroller systems uses XOR gates to compare address bits against expected patterns and assert a bank-select or chip-enable when a match occurs. With four independent XOR gates the SN74HC86NE4 can compare 4 address bits in a single DIP, generating an active-low chip-select for one memory bank out of sixteen possible 4-bit address patterns. Cascading two SN74HC86NE4 packages extends the technique to 8-bit address comparison for 256-bank decoding. The HC family's TTL-compatible inputs accept 5 V microcontroller or 3.3 V GPIO drive levels without external level shifters, and the CMOS outputs cleanly drive chip-enable and CS-bar inputs of SRAM and flash memory devices.
Recomendado
Comparator / Equality Detector
A multi-bit equality detector cascades XOR gates followed by a NOR gate: each XOR compares one bit pair and outputs 0 when equal, and the NOR output is HIGH only when all compared bits are equal. Two SN74HC86NE4 packages provide an 8-bit equality comparator in just four ICs - one to compare each bit pair and one to NOR the results. This comparator is widely used in address-recognition logic, hardware security tag readers, and data-validation circuits. The SN74HC86NE4's wide 2-6 V supply range supports battery-powered sensor front-ends operating from 3.3 V rails while maintaining TTL input compatibility with upstream 5 V signaling where required.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para SN74HC86NE4 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | SN74HC86N | MC74HC86ANG | MC74HC86AN | CD4070BE | CD4030BE |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | onsemi | onsemi | Texas Instruments | Texas Instruments |
| Package | 14-PDIP (N) | 14-PDIP (N) | 14-PDIP (N) | 14-PDIP (N) | 14-PDIP (N) | 14-PDIP (N) |
| Logic Family | HC (High-Speed CMOS) | HC (same) | HC (same) | HC (same) | 4000-series CMOS | 4000-series CMOS |
| Operating Voltage (VCC) | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V | 3 V to 18 V | 3 V to 15 V |
| Propagation Delay (typ, 5 V) | 6 ns @ 5 V / 50 pF | 6 ns (same) | ~7 ns | ~7 ns | ~120 ns @ 10 V | ~125 ns @ 10 V |
| Output Drive Current | 5.2 mA | 5.2 mA (same) | 5.2 mA (same) | 5.2 mA (same) | 1 mA (typ) | 1 mA (typ) |
| Output Type | CMOS push-pull | CMOS push-pull | CMOS push-pull | CMOS push-pull | CMOS push-pull | CMOS push-pull |
| Pb-Free / RoHS | Yes (NE4 suffix) | No (Pb-bearing N suffix) | Yes (G suffix) | No (Pb-bearing N suffix) | Yes (E suffix) | Yes (E suffix) |
Principais diferenciais
- Pb-free / RoHS compliant drop-in for legacy SN74HC86N (vs SN74HC86N)
- Wide 2-6 V operating range supports mixed-voltage designs (vs CD4070BE (4000-series CMOS))
- 5.2 mA CMOS drive strength versus 1 mA in 4000-series (vs CD4070BE / CD4030BE)
Notas de projeto
Always tie unused inputs directly to VCC or GND. Floating HC inputs drift into linear operation, drawing milliamps of quiescent current from each gate and potentially causing logic oscillations that inject supply noise into nearby analog circuits. A direct connection is preferred over pull-up/pull-down resistors because resistors introduce voltage drop from input leakage current. According to TI application guidance for the 74HC family, never leave inputs unconnected even when the gate output is unused.
Decouple VCC to GND with a 100 nF ceramic capacitor placed within 5 mm of pin 14 on every SN74HC86NE4. The HC family has high-edge-rate CMOS outputs (approximately 1 ns rise/fall at 5 V), and inadequate decoupling causes ground-bounce and supply-rail collapse during simultaneous-output switching. For multi-gate packages driving heavy capacitive loads, add a bulk 1-10 µF tantalum or aluminum electrolytic capacitor adjacent to the device. Decoupling minimizes the effect of Ldi/dt switching transients in bus-driving applications.
Do not apply input voltages greater than VCC + 0.5 V, or greater than 7 V absolute maximum, even though the inputs have clamp diodes to VCC. When driving HC inputs from a higher-voltage source (such as a 12 V analog front-end), use a series resistor (10-100 kΩ) to limit fault current through the input clamp diodes and prevent latent damage from over-voltage transients. Per TI datasheet absolute maximum ratings, input clamp current should be limited to ±20 mA to avoid long-term reliability degradation.
Informações de conformidade
RoHS compliant per NE4 Pb-free assembly designation. Not AEC-Q100 qualified (this is a commercial/industrial logic IC, not an automotive-qualified product). NiPdAu lead finish, halogen-free per JESD709.
