TPS51640RSLR - 2+1 IMVP7 CPU/GPU Controller | Texas Instruments
N.º da peça: TPS51640RSLR ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $4.2 | $4,20 |
| 10 | $3.78 | $37,80 |
| 100 | $3.36 | $336,00 |
| 500 | $3.02 | $1.510,00 |
| 1.000 | $2.69 | $2.690,00 |
| 3.000 | $2.35 | $7.050,00 |
TPS51640RSLR Visão geral
An SVID (Serial VID) interface and an IMVP7 (Intel Mobile Voltage Positioning 7) controller is a digital protocol that lets a CPU or GPU set its own operating voltage on the fly. The 2+1 phase topology distributes thermal stress across three inductor-switch pairs for the CPU rail (sharing up to ~80A of load with proper external MOSFETs) while a single phase handles graphics output. A D-CAP+ modulator with on-resistance current sensing eliminates the need for external shunt resistors, reducing BOM cost and PCB area. The integrated bootstrap switch and driver-less architecture require external high-side and low-side MOSFETs.
Key features include 0.5% Vout accuracy, selectable 250 kHz to 1.5 MHz per-phase switching frequency, dynamic phase shedding from 3-phase to 1-phase to optimize light-load efficiency, programmable soft-start, and comprehensive protection including OVP, UVP, OCP and thermal shutdown. The thermal pad and 48-pin QFN layout provide a theta-JA near 28 C/W on a 4-layer PCB.
Typical applications include IMVP7-compliant mobile computing platforms, ultrabook main rails, Ultrabook/Chromebook CPU VCORE rails, and 2-in-1 convertible tablet main rails. Industrial variants may use the controller with appropriate external components for any multi-phase CPU/GPU voltage regulation scheme that supports SVID protocol.
When designing with the TPS51640RSLR, current-loop compensation components (R-C-C) must be selected based on the per-phase inductance and selected switching frequency. The SVID address and VR enable polarity must be configured during platform design with the CPU vendor. The TPS51640RSLR is functionally identical to the TPS51640A (which has different boot voltage specifications per datasheet).
Alternativas drop-in para TPS51640RSLR — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
TPS51640ARSLR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
TPS59640RSLR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
TPS59641RSLR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
TPS51640RSLR Classificações máximas e características elétricas
| Topologia | 2+1 phase step-down (3-phase CPU + 1-phase GPU controller) |
| Faixa de tensão de saída | 0.25 V to 1.5 V (programmable via SVID) |
| Output Voltage Accuracy | 0.5% (across load, line and temperature) |
| Faixa de tensão de entrada | 4.5 V to 28 V |
| Frequência de comutação | 250 kHz to 1.5 MHz per phase (programmable) |
| Number of Phases | 2+1 (two rails; CPU up to 3 phases, GPU single phase) |
| Modulation Scheme | D-CAP+ with on-resistance current sensing |
| Communication Interface | SVID (Serial VID) for IMVP7 compliance |
| Tensão de referência | 1.0 V internal reference |
| Soft-start | Programmable |
| Temperatura de operação | -10 C to +105 C |
| Encapsulamento | 48-pin QFN (RSL), 7x7 mm with thermal pad |
| Tipo de montagem | Surface Mount |
| Nível MSL | 2 |
| Status RoHS | Compliant |
| Protections | OVP, UVP, OCP, Thermal Shutdown |
Configuração de pinos do TPS51640RSLR
| Pino 1 | VCC — Internal LDO bypass / 5V analog supply |
| Pino 2 | EN — Active-high controller enable |
| Pino 3 | SVID_DATA — SVID serial data (open-drain) |
| Pino 4 | SVID_CLK — SVID serial clock (input) |
| Pino 5 | SVID_ALERT — SVID alert from CPU (open-drain) |
| Pino 6 | VR_HOT — Thermal hot flag output |
| Pino 7 | VSNS_CPU — Vout sense for CPU rail (negative) |
| Pino 8 | VSNS_CPU_P — Vout sense for CPU rail (positive) |
| Pino 9 | CS1N — Channel 1 current sense negative |
| Pino 10 | CS1P — Channel 1 current sense positive |
| Pino 11 | BOOT1 — Phase 1 bootstrap |
| Pino 12 | UGATE1 — Phase 1 high-side gate drive |
| Pino 13 | LGATE1 — Phase 1 low-side gate drive |
| Pino 14 | VSW1 — Phase 1 switch node |
| Pino 15 | PGND1 — Phase 1 power ground |
| Pino 16 | BOOT2 — Phase 2 bootstrap |
| Pino 17 | UGATE2 — Phase 2 high-side gate drive |
| Pino 18 | LGATE2 — Phase 2 low-side gate drive |
| Pino 19 | VSW2 — Phase 2 switch node |
| Pino 20 | PGND2 — Phase 2 power ground |
| Pino 21 | BOOT3 — Phase 3 bootstrap (CPU rail phase 3) |
| Pino 22 | UGATE3 — Phase 3 high-side gate drive |
| Pino 23 | LGATE3 — Phase 3 low-side gate drive |
| Pino 24 | VSW3 — Phase 3 switch node |
| Pino 25 | PGND3 — Phase 3 power ground |
| Pino 26 | VID_SET — External VID configuration |
| Pino 27 | VR_RDY — Power-good output to CPU |
| Pino 28 | OVP — Over-voltage protection input |
| Pino 29 | UVP — Under-voltage protection input |
| Pino 30 | OCP — Over-current protection threshold |
| Pino 31 | ILIM — Per-phase current-limit setting |
| Pino 32 | FREQ — Switching frequency trim resistor |
| Pino 33 | RT — Timing resistor (frequency set) |
| Pino 34 | COMP1 — Compensation node phase 1 |
| Pino 35 | COMP2 — Compensation node phase 2 |
| Pino 36 | COMP3 — Compensation node phase 3 |
| Pino 37 | VSNS_GPU — Vout sense for GPU rail (negative) |
| Pino 38 | VSNS_GPU_P — Vout sense for GPU rail (positive) |
| Pino 39 | BOOT4 — GPU rail phase bootstrap |
| Pino 40 | UGATE4 — GPU rail high-side gate drive |
| Pino 41 | LGATE4 — GPU rail low-side gate drive |
| Pino 42 | VSW4 — GPU rail switch node |
| Pino 43 | PGND4 — GPU rail power ground |
| Pino 44 | REF — Internal reference 1.0V bypass |
| Pino 45 | AGND — Analog ground |
| Pino 46 | TRK — Soft-start / voltage tracking |
| Pino 47 | SET5 — VID table select |
| Pino 48 | PAD — Thermal pad / PGND (must be soldered) |
Aplicações típicas
TPS51640RSLR é adequado para 6 aplicaçãos: IMVP7 Ultrabook CPU VCORE Rail, Mobile GPU Voltage Regulator, 2-in-1 Tablet Main Rail, Intel Y/U-Series Notebook Power, Industrial IMVP7-Compatible Embedded Platform, Server Memory/Voltage-Positioned Auxiliary Rail.
IMVP7 Ultrabook CPU VCORE Rail
The TPS51640RSLR is purpose-built for IMVP7-compliant Intel ultrabook CPU rails. With 0.5% Vout accuracy, SVID command compliance, and a 2+1 phase topology the part shares three phases across the CPU rail so each phase handles ~30A of sub-1V load. D-CAP+ modulation delivers sub-100 ns transient response with no external compensation network, which is critical when the CPU jumps between C-states. Phase shedding from 3 to 1 phase holds light-load efficiency above 80% at 0.7V Vout, extending battery run-time during idle.
Recomendado
Mobile GPU Voltage Regulator
The second rail of the TPS51640RSLR drives integrated Intel GPUs in a single-phase configuration. The 0.25V minimum output enables sub-1V GPU VCORE operation needed for energy-efficient graphics. By sharing the same SVID bus the GPU rail coordinates load-line with the CPU rail so transient events on one rail do not sag the other. Internal adaptive on-resistance current sensing removes external shunt resistors, reducing PCB area - a meaningful gain for sub-2 mm Z-height ultrabook chassis.
Recomendado
2-in-1 Tablet Main Rail
The 2+1 architecture of the TPS51640RSLR simultaneously powers the SoC and its companion GPU in compact 2-in-1 tablet and Chromebook designs. With switching frequency programmable from 250 kHz to 1.5 MHz per phase, the designer can shrink output inductors to 0.47 uH to fit the 4 mm x 4 mm CPU land area. The -10 C to +105 C operating range covers cold-boot and warm-tablet conditions without thermal derating, while the 28 C/W theta-JA from the 48-QFN thermal pad spreads heat into a copper plane.
Recomendado
Intel Y/U-Series Notebook Power
For Intel Y-series and U-series processors, the TPS51640RSLR implements SVID voltage identification, load-line, and adaptive thermal management required by Intel IMC firmware. Per-phase switching up to 1.5 MHz keeps the converter above the AM-band, reducing audible noise and easing filter design. Programmable soft-start prevents inrush at 0.5%-accuracy cold-boot scenarios. This positions the controller as a turnkey solution for 9-15 W TDP notepads and slim notebooks.
Recomendado
Industrial IMVP7-Compatible Embedded Platform
Outside the mainstream laptop market, the TPS51640RSLR is used in industrial IMVP7-derived SBCs and panel PCs that need multi-phase SVID control. The wide 4.5V-28V input range accepts 12V/24V industrial rails through a preregulator, and the 0.5% Vout accuracy supports AI vision, embedded GPU and edge inferencing workloads. Protections (OVP/UVP/OCP/Thermal Shutdown) reduce BOM by replacing several discrete supervisor devices.
Recomendado
Server Memory/Voltage-Positioned Auxiliary Rail
Although designed for IMVP7 CPUs, designers have adapted the TPS51640RSLR for voltage-positioned memory rails where 0.5% accuracy and D-CAP+ dynamic performance are valuable. The two rails (3-phase + 1-phase) provide enough flexibility to drive DDR terminators or auxiliary cores, and the 1.0V internal reference enables sub-1V output. This is a derivative, non-IMVP7 use case - firmware must bypass SVID to a fixed VID command set.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para TPS51640RSLR — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | TPS51640ARSLR | TPS59640RSLR | TPS59641RSLR |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-QFN (RSL) 7x7 mm | 48-QFN (RSL) 7x7 mm - same | 48-QFN (RSL) 7x7 mm - same | 48-QFN (RSL) 7x7 mm - same |
| Topology | 2+1 phase (CPU 3-phase + GPU 1-phase) | 2+1 phase | 2+1 phase | 2+1 phase |
| IMVP Compliance | IMVP7 | IMVP7 | IMVP6.5 | IMVP6.5 |
| V_BOOT Voltage | 1.1 V | 0 V | 0 V | 1.1 V |
| Output Voltage Accuracy | 0.5% | 0.5% | 0.5% | 0.5% |
| Switching Frequency Range | 250 kHz to 1.5 MHz | 250 kHz to 1.5 MHz | 250 kHz to 1.5 MHz | 250 kHz to 1.5 MHz |
| Operating Temperature | -10 C to +105 C | -10 C to +105 C | -40 C to +105 C | -40 C to +105 C |
Principais diferenciais
- Original V_BOOT = 1.1V for legacy CPU platforms (vs TPS51640ARSLR)
- Wider operating temperature floor than IMVP6.5 series (vs TPS59640RSLR)
- IMVP7 SVID command set vs older IMVP6.5 (vs TPS59640RSLR / TPS59641RSLR)
Notas de projeto
Estimated: at full 3-phase CPU load of ~80A with Vout=0.8V and Vin=12V, total dissipation across external high-/low-side MOSFETs and the controller can reach 6W. The 48-pin QFN (RSL) has a typical theta_JA near 28 C/W on a 4-layer 2-oz copper PCB; assume junction-to-ambient rise near 170C at 6W. Use at least 1 square inch of copper array under the thermal pad plus thermal vias to inner planes to keep Tj below 105C.
Route the SVID bus lines (SVID_DATA, SVID_CLK, SVID_ALERT) as a 50 ohm microstrip on inner layers or guarded by GND to avoid jitter on the ~26 MHz clock. Place the per-phase bootstrap capacitor (BOOTx-PGND) within 5 mm of the IC. The current-sense traces (CS1N, CS1P, CS2N, CS2P, CS3N, CS3P, CSP, CSN) must be kelvin-connected to the low-side FET pads to preserve D-CAP+ accuracy.
Do not skip the REF 1.0V bypass capacitor (1 uF X7R minimum) - it sets the DAC reference for all VID commands. Ensure VR_RDY is correctly pulled up to PCH's 3.3V rail, otherwise the CPU will not release POST and the platform will fail to boot. Never tie ILIM to VCC; an external resistor divider to AGND must set the per-phase current limit. The SVID address is hard-coded - if two controllers share a bus, SVID_ALERT collisions will occur.
Informações de conformidade
RoHS compliant per TI product page; not AEC-Q100 qualified - no automotive-grade equivalent exists in this family.
