EP610PC-30 vs EP610PC-20 Сравнение
Подробное сравнение бок о бок EP610PC-30 от Altera и EP610PC-20 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP610PC-30 | EP610PC-20 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | NRND | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $27,74 | $47,80 |
| Device Family | Classic EPLD (EP610) | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 20 ns |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V ±10% |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Корпус | 24-pin PDIP (0.300 inch) | PDIP-24 |
| Тип монтажа | Through-Hole | — |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | — |
| Рабочая температура | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | — |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | — |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | — |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | — |
| Статус RoHS | Not applicable (legacy non-compliant package per distributor listing) | Non-compliant (legacy PDIP) |
| Lead Free Status | Not applicable | — |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | — |
| Family | — | Classic EPLD |
| Logic Elements | — | 16 macrocells |
| Maximum Operating Frequency | — | 100 MHz (pipelined) |
| Количество выводов | — | 24 |
| Programmable Flip-Flops | — | 16 |
| Input Pins | — | 24 |
| Output Pins | — | 16 |
| I/O Compatibility | — | TTL |
| Program/Erase Method | — | UV (windowed) or OTP |