EP610PC-30 vs EP610PC-20 对比
详细并排对比 EP610PC-30 出自 Altera 和 EP610PC-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610PC-30 | EP610PC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.74 | $47.80 |
| Device Family | Classic EPLD (EP610) | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 20 ns |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V ±10% |
| Process Technology | CMOS EPROM | CMOS EPROM |
| 封装 | 24-pin PDIP (0.300 inch) | PDIP-24 |
| 安装类型 | Through-Hole | — |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | — |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | — |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | — |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | — |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | — |
| RoHS 状态 | Not applicable (legacy non-compliant package per distributor listing) | Non-compliant (legacy PDIP) |
| Lead Free Status | Not applicable | — |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | — |
| Family | — | Classic EPLD |
| Logic Elements | — | 16 macrocells |
| Maximum Operating Frequency | — | 100 MHz (pipelined) |
| 引脚数 | — | 24 |
| Programmable Flip-Flops | — | 16 |
| Input Pins | — | 24 |
| Output Pins | — | 16 |
| I/O Compatibility | — | TTL |
| Program/Erase Method | — | UV (windowed) or OTP |