EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
Артикул: EPM7128AETC100-10N ✗ Снят с производства| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1.385,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.95 | $9.950,00 |
EPM7128AETC100-10N Обзор
A CPLD is a non-volatile, instant-on programmable logic device that combines the deterministic timing of PAL/PLA architectures with the density of small FPGAs, sitting between discrete glue logic and full FPGAs in the system hierarchy. The MAX 7000AE series belongs to the broader programmable logic family, which scales from these 32-to-512-macrocell CPLDs up to modern high-density FPGAs; CPLDs are preferred when deterministic propagation delay, single-chip non-volatile boot, and simple JTAG-based ISP are required without the need for an external configuration memory.
Key features include 128 macrocells with 16 logic array blocks, 84 user I/O pins, 3.3V core operation with 5.0V tolerant I/O, and an extended commercial temperature range. Each macrocell contains a programmable AND/OR array with a configurable register that can be bypassed for combinational logic or retained for sequential state machines. The device also includes four JTAG-compliant pins (TDI, TDO, TMS, TCK) supporting boundary-scan test and in-system programming.
The MAX architecture implements a global interconnect fabric that routes signals between Logic Array Blocks (LABs) with predictable timing, eliminating the routing-delay variability seen in SRAM-based FPGAs. The non-volatile EEPROM cells retain the programmed logic across power cycles, providing instant-on behavior at sub-microsecond times, which is critical in industrial control and PCI bus glue applications where the host processor expects deterministic configuration before reset deassertion.
Typical applications include PCI bus interface glue logic, glue logic for microprocessor and DSP systems, bus decoding and address mapping, state-machine controllers, and 5V-to-3.3V translation bridges. Industrial and telecom equipment designs frequently pair the EPM7128AE with host processors to implement custom peripherals, bus arbitration, and timing-sensitive I/O expansion.
When designing with this device, note that the 'N' suffix denotes lead-free / Pb-free assembly. Designers migrating from older 5V MAX 7000S parts must verify input-threshold compatibility because the AE core operates at 3.3V while outputs are 5V tolerant only with external pull-up. Always consult the MAX 7000AE Programmable Logic Device Family Data Sheet for timing model details.
This page synthesizes distributor pricing, parametric alternatives, and practical design notes not found in the manufacturer datasheet.
Аналоги без доработки для EPM7128AETC100-10N — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с EPM7128AETC100-10N (тот же форм-фактор и посадочное место) — отличается по Package, Operating Temperature, Family, Process Technology, JTAG Support.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
EPM7128AETC100-10
✅ Прямая замена✓ В наличии
$13.85 / шт.
Открыть даташит →EPM7128AET1100-7
✅ Прямая замена✓ В наличии
$16.4 / шт.
Открыть даташит →EPM7128AEFC100-5
✅ Прямая замена✓ В наличии
$79.5 / шт.
Открыть даташит →EPM570T100C5N
✅ Прямая замена ⚠️ Характеристики не проверены✓ В наличии
$10.2 / шт.
Открыть даташит →EPM570GT100C5N
✅ Прямая замена ⚠️ Характеристики не проверены✓ В наличии
$11.05 / шт.
Открыть даташит →EPM570T100I5N
✅ Прямая замена ⚠️ Характеристики не проверены✓ В наличии
$12.49 / шт.
Открыть даташит →EPM7128AETC100-10N Максимальные параметры и электрические характеристики
| Family | MAX 7000AE |
| Series | EPM7128AE |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Usable Gates | 2500 |
| Logic Array Blocks | 16 |
| User I/Os | 84 |
| Supply Voltage (Core) | 3.3 V |
| I/O Tolerance | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Speed Grade | -10 |
| Корпус | TQFP-100 |
| Тип монтажа | Surface Mount |
| Programming | JTAG (IEEE 1149.1) ISP / EEPROM |
| Рабочая температура | 0C to +70C (commercial) |
| Lead-Free / RoHS | Yes (N suffix) |
| Process Technology | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | Yes (33 MHz, -10 grade per PCI SIG 2.2) |
Конфигурация выводов EPM7128AETC100-10N
| Контакт 1 | I/O — User I/O pin (LAB A) |
| Контакт 2 | I/O — User I/O pin (LAB A) |
| Контакт 3 | I/O — User I/O pin (LAB A) |
| Контакт 4 | I/O — User I/O pin (LAB A) |
| Контакт 5 | I/O — User I/O pin (LAB A) |
| Контакт 6 | I/O — User I/O pin (LAB A) |
| Контакт 7 | VCCINT — 3.3V core supply |
| Контакт 8 | I/O — User I/O pin (LAB A) |
| Контакт 9 | I/O — User I/O pin (LAB A) |
| Контакт 10 | I/O — User I/O pin (LAB A) |
| Контакт 11 | I/O — User I/O pin (LAB A) |
| Контакт 12 | GND — Ground |
| Контакт 13 | I/O — User I/O pin (LAB A) |
| Контакт 14 | I/O — User I/O pin (LAB A) |
| Контакт 15 | I/O — User I/O pin (LAB A) |
| Контакт 16 | I/O — User I/O pin (LAB A) |
| Контакт 17 | I/O — User I/O pin (LAB B) |
| Контакт 18 | I/O — User I/O pin (LAB B) |
| Контакт 19 | I/O — User I/O pin (LAB B) |
| Контакт 20 | I/O — User I/O pin (LAB B) |
| Контакт 21 | GND — Ground |
| Контакт 22 | I/O — User I/O pin (LAB B) |
| Контакт 23 | I/O — User I/O pin (LAB B) |
| Контакт 24 | I/O — User I/O pin (LAB B) |
| Контакт 25 | I/O — User I/O pin (LAB B) |
| Контакт 26 | VCCIO — I/O supply voltage |
| Контакт 27 | I/O — User I/O pin (LAB B) |
| Контакт 28 | I/O — User I/O pin (LAB B) |
| Контакт 29 | I/O — User I/O pin (LAB B) |
| Контакт 30 | I/O — User I/O pin (LAB C) |
| Контакт 31 | I/O — User I/O pin (LAB C) |
| Контакт 32 | I/O — User I/O pin (LAB C) |
| Контакт 33 | I/O — User I/O pin (LAB C) |
| Контакт 34 | GND — Ground |
| Контакт 35 | I/O — User I/O pin (LAB C) |
| Контакт 36 | I/O — User I/O pin (LAB C) |
| Контакт 37 | I/O — User I/O pin (LAB C) |
| Контакт 38 | I/O — User I/O pin (LAB C) |
| Контакт 39 | I/O — User I/O pin (LAB C) |
| Контакт 40 | VCCINT — 3.3V core supply |
| Контакт 41 | I/O — User I/O pin (LAB C) |
| Контакт 42 | I/O — User I/O pin (LAB C) |
| Контакт 43 | I/O — User I/O pin (LAB C) |
| Контакт 44 | I/O — User I/O pin (LAB D) |
| Контакт 45 | I/O — User I/O pin (LAB D) |
| Контакт 46 | I/O — User I/O pin (LAB D) |
| Контакт 47 | I/O — User I/O pin (LAB D) |
| Контакт 48 | GND — Ground |
| Контакт 49 | I/O — User I/O pin (LAB D) |
| Контакт 50 | I/O — User I/O pin (LAB D) |
| Контакт 51 | I/O — User I/O pin (LAB D) |
| Контакт 52 | I/O — User I/O pin (LAB D) |
| Контакт 53 | I/O — User I/O pin (LAB D) |
| Контакт 54 | VCCIO — I/O supply voltage |
| Контакт 55 | I/O — User I/O pin (LAB D) |
| Контакт 56 | I/O — User I/O pin (LAB D) |
| Контакт 57 | I/O — User I/O pin (LAB E) |
| Контакт 58 | I/O — User I/O pin (LAB E) |
| Контакт 59 | I/O — User I/O pin (LAB E) |
| Контакт 60 | I/O — User I/O pin (LAB E) |
| Контакт 61 | GND — Ground |
| Контакт 62 | I/O — User I/O pin (LAB E) |
| Контакт 63 | I/O — User I/O pin (LAB E) |
| Контакт 64 | I/O — User I/O pin (LAB E) |
| Контакт 65 | I/O — User I/O pin (LAB E) |
| Контакт 66 | I/O — User I/O pin (LAB E) |
| Контакт 67 | VCCINT — 3.3V core supply |
| Контакт 68 | I/O — User I/O pin (LAB E) |
| Контакт 69 | I/O — User I/O pin (LAB F) |
| Контакт 70 | I/O — User I/O pin (LAB F) |
| Контакт 71 | I/O — User I/O pin (LAB F) |
| Контакт 72 | I/O — User I/O pin (LAB F) |
| Контакт 73 | GND — Ground |
| Контакт 74 | I/O — User I/O pin (LAB F) |
| Контакт 75 | I/O — User I/O pin (LAB F) |
| Контакт 76 | I/O — User I/O pin (LAB F) |
| Контакт 77 | I/O — User I/O pin (LAB F) |
| Контакт 78 | I/O — User I/O pin (LAB G) |
| Контакт 79 | I/O — User I/O pin (LAB G) |
| Контакт 80 | VCCIO — I/O supply voltage |
| Контакт 81 | I/O — User I/O pin (LAB G) |
| Контакт 82 | I/O — User I/O pin (LAB G) |
| Контакт 83 | I/O — User I/O pin (LAB G) |
| Контакт 84 | I/O — User I/O pin (LAB G) |
| Контакт 85 | I/O — User I/O pin (LAB H) |
| Контакт 86 | I/O — User I/O pin (LAB H) |
| Контакт 87 | I/O — User I/O pin (LAB H) |
| Контакт 88 | GND — Ground |
| Контакт 89 | I/O — User I/O pin (LAB H) |
| Контакт 90 | I/O — User I/O pin (LAB H) |
| Контакт 91 | I/O — User I/O pin (LAB H) |
| Контакт 92 | DEV_OE — Device-wide output enable (active low) |
| Контакт 93 | DEV_CLRn — Device-wide clear (active low) |
| Контакт 94 | GCLK — Global clock input |
| Контакт 95 | TDO — JTAG test data output |
| Контакт 96 | TMS — JTAG test mode select |
| Контакт 97 | TCK — JTAG test clock |
| Контакт 98 | TDI — JTAG test data input |
| Контакт 99 | I/O — User I/O pin (LAB H) |
| Контакт 100 | I/O — User I/O pin (LAB H) |
Типичное применение
EPM7128AETC100-10N подходит для 6 применениеs: PCI Bus Interface Glue Logic, Microprocessor / DSP System Glue Logic, Bus Address Decoding and Mapping, State-Machine Controllers, 5V-to-3.3V Logic Translation Bridges, Telecom and Network Equipment Glue Logic.
PCI Bus Interface Glue Logic
The EPM7128AETC100-10N is widely deployed as PCI bus glue logic between 33 MHz host chipsets and peripheral devices, where its 10 ns pin-to-pin delay and 84 user I/Os are tuned to PCI Local Bus Specification Revision 2.2 timing. The device's JTAG boundary-scan support simplifies PCI compliance testing, while the 5V-tolerant I/O buffers allow direct interface to legacy 5V PCI peripherals. With 128 macrocells, designers can implement address decoding, bus arbitration, command/byte-enable decoding, and parity generation within a single device, eliminating discrete 74-series glue. The MAX 7000AE non-volatile EEPROM technology provides instant-on configuration, eliminating the FPGA-style external boot PROM that would otherwise violate PCI reset sequencing timing.
Рекомендуется
Microprocessor / DSP System Glue Logic
Designers pair the EPM7128AETC100-10N with microprocessors and DSPs to implement custom peripherals, wait-state generators, chip-select decoding, and bus-interface bridges. The CPLD's 84 user I/Os comfortably accommodate 16-bit data buses plus 24-bit address and control signal routing, while 128 macrocells provide ample capacity for address decoding, interrupt control, and FIFOs. Because the part retains its configuration in EEPROM, the host CPU sees a deterministic, instant-on logic block at reset without the boot latency of SRAM-based FPGAs. Industrial PC/104, VME, and embedded SBC designs historically leverage the MAX 7000AE family for this role.
Рекомендуется
Bus Address Decoding and Mapping
The 128 macrocells of the EPM7128AETC100-10N are well-suited to multi-bank address decoding for memory and peripheral subsystems, particularly in 8-bit, 16-bit, and 32-bit microprocessor designs. Designers implement large AND-OR decoder planes that activate chip-select lines based on address ranges and bank-switch logic, replacing dozens of discrete 74LS138/139 decoders. The 10 ns tPD keeps decoded chip-selects stable well within typical microprocessor access-time budgets. JTAG ISP allows late-stage board-bring-up changes to the address map without respinning the PCB.
Рекомендуется
State-Machine Controllers
Industrial control and instrumentation systems use the EPM7128AETC100-10N as a deterministic state-machine controller for sequencing, fault handling, and protocol bridging. Unlike microcontrollers, the CPLD executes state transitions in parallel hardware with sub-10ns response times, making it ideal for sensor-fusion and safety-critical sequencing where interrupt latency would be unacceptable. Each macrocell provides a configurable D/T/JK flip-flop, and 128 macrocells support FSMs with 50+ states plus combinatorial glue logic. The 5V-tolerant I/Os simplify connection to legacy industrial sensors and actuators.
Рекомендуется
5V-to-3.3V Logic Translation Bridges
The EPM7128AETC100-10N operates from a 3.3V core while its I/O buffers are 5V-tolerant, making it ideal as a level-translation bridge between 5V legacy peripherals and 3.3V processors. Designers route 5V signals through the input pins (which tolerate 5V when VCCIO = 3.3V) and produce 3.3V outputs to the host CPU, replacing dedicated level-shifter ICs. With 84 user I/Os, the device can translate 8- or 16-bit data buses plus control signals in a single chip. JTAG ISP enables late-stage configuration of direction-control logic without hardware changes.
Рекомендуется
Telecom and Network Equipment Glue Logic
Telecom and networking platforms historically deployed the EPM7128AETC100-10N for TDM bus arbitration, E1/T1 framing logic, and backplane glue between line cards and switch fabrics. The CPLD's deterministic timing suits SONET/SDH-derived line rates where jitter budgets are tight, while the JTAG boundary-scan simplifies board-level test on densely populated backplanes. With 128 macrocells, designers can implement multiple independent glue-logic functions (clock distribution, frame alignment, alarm generation) in a single device. The commercial 0-70C temperature range suits central-office equipment environments.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для EPM7128AETC100-10N — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | EPM7128AETC100-10 | EPM7128AET1100-7 | EPM7128AEFC100-5 | EPM570T100C5N |
|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Family | MAX 7000AE | MAX 7000AE | MAX 7000AE | MAX 7000AE | MAX II |
| Macrocells | 128 | 128 | 128 | 128 | 570 |
| User I/Os | 84 | 84 | 84 | 84 | 76 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 7 ns | 5 ns | 5 ns (MAX II) |
| Supply Voltage (Core) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V (2.5V option) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Active |
| Programming | JTAG ISP / EEPROM | JTAG ISP / EEPROM | JTAG ISP / EEPROM | JTAG ISP / EEPROM | JTAG ISP / Flash |
Ключевые отличия
- Drop-in faster speed-grade option in same TQFP-100 footprint (против EPM7128AETC100-7)
- Non-volatile EEPROM configuration eliminates boot PROM (против SRAM-based FPGAs)
- 5V-tolerant I/O on a 3.3V core (против MAX II EPM570T100C5N)
Заметки по проектированию
The EPM7128AETC100-10N requires separate VCCINT (3.3V core) and VCCIO (I/O supply, typically 3.3V) rails. Decouple each VCCINT and VCCIO pin with a 0.1uF ceramic capacitor placed within 5mm of the pin, and add a bulk 10uF tantalum or ceramic capacitor near each supply pin group. Power-up sequencing is not critical because internal POR circuitry holds the device in reset until VCCINT stabilizes. The 'N' suffix indicates lead-free (Pb-free) matte-tin finish compatible with lead-free reflow profiles up to 260C peak.
Route JTAG signals (TCK, TMS, TDI, TDO) with characteristic impedance of 50 ohms and keep them short to minimize reflections. Place a 10kohm pull-up on TCK and TMS to ensure defined logic levels during cable disconnect; TDO is high-impedance when not shifting and does not require a pull-up. Reserve a JTAG header or test-pad access on the PCB even if programming is performed only at board assembly - field firmware updates are common. Keep global clock (GCLK) traces short and routed away from high-speed I/O to minimize crosstalk into the clock domain.
A common pitfall is assuming the 5V-tolerant I/O outputs 5V levels - the I/O buffers drive to VCCIO (typically 3.3V), not 5V. To interface with 5V logic inputs, the EPM7128AE outputs can drive 5V CMOS inputs if VCCIO = 3.3V and the receiver has TTL-compatible thresholds, but not true 5V CMOS levels. Another pitfall is neglecting the in-system programming cycle time (typically 1-3 seconds via JTAG) - production test fixtures must allow this delay. Finally, verify the Quartus II software version supports the specific -10 speed grade before compiling legacy designs, because some newer Quartus releases deprecate older MAX device timing models.
The TQFP-100 package has a typical theta_JA of approximately 50 C/W in still air, allowing continuous operation up to about 0.8W dissipation at 25C ambient. For designs with high toggle rates across all 84 I/Os, estimate dynamic power at approximately P_dynamic = C_load * VCCIO^2 * f * N, where N is the number of switching outputs; for typical 25 MHz operation on 50 outputs with 30pF load this is approximately 0.4W. Add copper thermal relief under the TQFP-100 package on inner PCB layers if the design operates near the upper commercial temperature limit (70C).
Информация о соответствии
Lead-free / Pb-free matte-tin finish per the N suffix. RoHS compliant per distributor product pages. AEC-Q100 not applicable - this is a commercial-grade CPLD, not an automotive-qualified part. Operating temperature range is 0C to +70C commercial.