EPM570T100C5N - MAX II 570 LE CPLD, 100-TQFP | Intel (Altera)
MPN: EPM570T100C5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16.55 | $16.55 |
| 10 | $14.9 | $149.00 |
| 100 | $13.1 | $1,310.00 |
| 500 | $11.45 | $5,725.00 |
| 1,000 | $10.2 | $10,200.00 |
Drop-in alternatives for EPM570T100C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570T100C4N
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View Datasheet →EPM570T100A5N
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View Datasheet →EPM570T100I5N
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$12.49 / Unit
View Datasheet →EPM570T100C3N
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$8.1 / Unit
View Datasheet →EPM570M100C5N
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$11.85 / Unit
View Datasheet →EPM570T100C5N Maximum Ratings & Electrical Characteristics
| Series | MAX II |
| Family | CPLD - MAX II |
| Logic Elements (LE) | 570 |
| Macrocells | 440 |
| User I/Os | 76 |
| User Flash Memory | 8 Kbit |
| Process Technology | 0.18 µm 6-layer-metal Flash |
| Internal Performance | 201.1 MHz |
| Supply Voltage | 2.5 V / 3.3 V |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Package | 100-pin TQFP (T100) |
| Mounting Type | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| I/O Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt |
| RoHS Status | Compliant |
EPM570T100C5N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O pin |
| Pin 2 | I/O — General-purpose user I/O pin |
| Pin 3 | I/O — General-purpose user I/O pin |
| Pin 4 | I/O — General-purpose user I/O pin |
| Pin 5 | I/O — General-purpose user I/O pin |
| Pin 6 | I/O — General-purpose user I/O pin |
| Pin 7 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 8 | I/O — General-purpose user I/O pin |
| Pin 9 | I/O — General-purpose user I/O pin |
| Pin 10 | I/O — General-purpose user I/O pin |
| Pin 11 | I/O — General-purpose user I/O pin |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — General-purpose user I/O pin |
| Pin 14 | I/O — General-purpose user I/O pin |
| Pin 15 | I/O — General-purpose user I/O pin |
| Pin 16 | I/O — General-purpose user I/O pin |
| Pin 17 | I/O — General-purpose user I/O pin |
| Pin 18 | I/O — General-purpose user I/O pin |
| Pin 19 | I/O — General-purpose user I/O pin |
| Pin 20 | I/O — General-purpose user I/O pin |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — General-purpose user I/O pin |
| Pin 23 | I/O — General-purpose user I/O pin |
| Pin 24 | I/O — General-purpose user I/O pin |
| Pin 25 | I/O — General-purpose user I/O pin |
| Pin 26 | I/O — General-purpose user I/O pin |
| Pin 27 | I/O — General-purpose user I/O pin |
| Pin 28 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 29 | I/O — General-purpose user I/O pin |
| Pin 30 | I/O — General-purpose user I/O pin |
| Pin 31 | I/O — General-purpose user I/O pin |
| Pin 32 | I/O — General-purpose user I/O pin |
| Pin 33 | I/O — General-purpose user I/O pin |
| Pin 34 | I/O — General-purpose user I/O pin |
| Pin 35 | I/O — General-purpose user I/O pin |
| Pin 36 | I/O — General-purpose user I/O pin |
| Pin 37 | GND — Must be connected to GND (per EPM570-specific pinout) |
| Pin 38 | TDI — JTAG Test Data In |
| Pin 39 | VCCIO2 — Must be connected to 3.3V (per EPM570-specific pinout) |
| Pin 40 | TMS — JTAG Test Mode Select |
| Pin 41 | TCK — JTAG Test Clock |
| Pin 42 | TDO — JTAG Test Data Out |
| Pin 43 | I/O — General-purpose user I/O pin |
| Pin 44 | I/O — General-purpose user I/O pin |
| Pin 45 | I/O — General-purpose user I/O pin |
| Pin 46 | I/O — General-purpose user I/O pin |
| Pin 47 | I/O — General-purpose user I/O pin |
| Pin 48 | I/O — General-purpose user I/O pin |
| Pin 49 | I/O — General-purpose user I/O pin |
| Pin 50 | I/O — General-purpose user I/O pin |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — General-purpose user I/O pin |
| Pin 53 | I/O — General-purpose user I/O pin |
| Pin 54 | I/O — General-purpose user I/O pin |
| Pin 55 | I/O — General-purpose user I/O pin |
| Pin 56 | I/O — General-purpose user I/O pin |
| Pin 57 | I/O — General-purpose user I/O pin |
| Pin 58 | I/O — General-purpose user I/O pin |
| Pin 59 | I/O — General-purpose user I/O pin |
| Pin 60 | I/O — General-purpose user I/O pin |
| Pin 61 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 62 | I/O — General-purpose user I/O pin |
| Pin 63 | I/O — General-purpose user I/O pin |
| Pin 64 | I/O — General-purpose user I/O pin |
| Pin 65 | I/O — General-purpose user I/O pin |
| Pin 66 | I/O — General-purpose user I/O pin |
| Pin 67 | I/O — General-purpose user I/O pin |
| Pin 68 | I/O — General-purpose user I/O pin |
| Pin 69 | I/O — General-purpose user I/O pin |
| Pin 70 | I/O — General-purpose user I/O pin |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — General-purpose user I/O pin |
| Pin 73 | I/O — General-purpose user I/O pin |
| Pin 74 | I/O — General-purpose user I/O pin |
| Pin 75 | I/O — General-purpose user I/O pin |
| Pin 76 | I/O — General-purpose user I/O pin |
| Pin 77 | I/O — General-purpose user I/O pin |
| Pin 78 | I/O — General-purpose user I/O pin |
| Pin 79 | I/O — General-purpose user I/O pin |
| Pin 80 | I/O — General-purpose user I/O pin |
| Pin 81 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 82 | I/O — General-purpose user I/O pin |
| Pin 83 | I/O — General-purpose user I/O pin |
| Pin 84 | I/O — General-purpose user I/O pin |
| Pin 85 | I/O — General-purpose user I/O pin |
| Pin 86 | I/O — General-purpose user I/O pin |
| Pin 87 | I/O — General-purpose user I/O pin |
| Pin 88 | VCCIO3 — Must be connected to 3.3V (per EPM570-specific pinout) |
| Pin 89 | I/O — General-purpose user I/O pin |
| Pin 90 | GND — Must be connected to GND (per EPM570-specific pinout) |
| Pin 91 | I/O — General-purpose user I/O pin |
| Pin 92 | I/O — General-purpose user I/O pin |
| Pin 93 | I/O — General-purpose user I/O pin |
| Pin 94 | I/O — General-purpose user I/O pin |
| Pin 95 | I/O — General-purpose user I/O pin |
| Pin 96 | VCCINT — Internal core supply voltage (3.3V) |
| Pin 97 | I/O — General-purpose user I/O pin |
| Pin 98 | I/O — General-purpose user I/O pin |
| Pin 99 | I/O — General-purpose user I/O pin |
| Pin 100 | I/O — General-purpose user I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T100C5N is suitable for 6 applications: Microcontroller I/O Expansion and Bus Decoding, FPGA Configuration and Power Sequencing, Retro-Computing and Hobby Glue Logic, LED Driving and PWM Generation, ASIC/ASSP Replacement for EOL Parts, JTAG-Based Board Test and Boundary Scan.
Microcontroller I/O Expansion and Bus Decoding
The EPM570T100C5N's 570 logic elements and 76 user I/Os make it ideal for expanding microcontroller I/O counts and decoding address/data buses. Its deterministic pin-to-pin propagation delays and MultiVolt I/O allow direct interfacing with 3.3 V MCUs and 1.8 V peripherals in the same design. Instant-on non-volatile configuration eliminates boot-time delays, which is critical for real-time control loops where the MCU expects the CPLD's decoded chip-selects to be valid at reset release. The 8-Kbit user Flash can store revision IDs or serial numbers for board identification.
Recommended
FPGA Configuration and Power Sequencing
The EPM570T100C5N is widely used as a configuration watchdog and power sequencer for FPGAs and processors. Its JTAG interface can chain to downstream FPGAs for boundary-scan testing, while its programmable logic can enforce power-up/power-down sequencing across multiple rails. The 440 macrocells easily handle sequencing for 4-8 voltage rails, and the instant-on Flash-based configuration means the CPLD is alive before the main FPGA begins its configuration load, ready to gate resets and monitor PGOOD signals.
Recommended
Retro-Computing and Hobby Glue Logic
Retro-computing enthusiasts use the EPM570T100C5N to replace vintage 7400-series TTL glue logic with a single re-programmable chip. Its 570 logic elements and 76 I/Os can implement dozens of legacy 74xx functions in one device, simplifying board layout and reducing BOM count. The TQFP-100 package is breadboard-friendly with breakout boards, and the JTAG interface allows ISP reprogramming without removing the chip. Commercial temperature grade is sufficient for typical indoor hobby use, and the instant-on behavior matches the deterministic timing vintage CPUs expect.
Recommended
LED Driving and PWM Generation
The EPM570T100C5N generates multiple independent PWM channels for LED dimming, motor control, or fan speed regulation. Each macrocell can be configured as a free-running counter with programmable duty cycle, and the 201.1 MHz internal performance supports PWM frequencies well above the audible band to avoid motor whine. The MultiVolt I/O banks drive LED strings directly at 3.3 V or 5 V logic levels, and the 76 user I/Os can independently control up to 38 LED channels with current-limiting resistors.
Recommended
ASIC/ASSP Replacement for EOL Parts
Designers use the EPM570T100C5N as a drop-in functional replacement for obsolete ASICs or ASSPs in long-lifecycle products. Because the device is re-programmable, last-minute logic changes do not require a new silicon spin, accelerating time-to-market. The 440 macrocells and 76 I/Os cover most glue-logic integration tasks, while the commercial-grade temperature range suits industrial, medical, and consumer products. The MAX II family's 0.18 µm Flash process provides excellent data retention (>20 years) for field-deployed equipment.
Recommended
JTAG-Based Board Test and Boundary Scan
The EPM570T100C5N implements IEEE 1149.1 JTAG boundary-scan for production board test, allowing cluster testing of nets that are otherwise inaccessible with bed-of-nails fixtures. Its JTAG interface can be chained with other JTAG-compliant ICs on the board, and the on-chip user Flash can store board-test firmware that runs at power-on. The TQFP-100 package exposes all JTAG signals (TCK, TMS, TDI, TDO) plus the 76 user I/Os as boundary-scan cells, providing extensive fault coverage for shorts, opens, and stuck-at defects.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T100C5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T100C4N | EPM570T100A5N | EPM570T100I5N | EPM570T100C3N | EPM570M100C5N |
|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Speed Grade | C5 (fastest) | C4 (slower) | A5 (alternate) | I5 (industrial) | C3 (slowest) | C5 (equivalent) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| User I/Os | 76 | 76 | 76 | 76 | 76 | 76 |
| Internal Performance | 201.1 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | 201.1 MHz |
Key Differentiators
- Fastest speed grade in TQFP-100 footprint (vs EPM570T100C4N)
- Commercial temperature grade at lowest price (vs EPM570T100I5N)
- 570 logic elements vs smaller pin-compatible variants (vs EPM240T100C5N)
Design Notes
The EPM570T100C5N requires a stable 3.3 V supply on VCCINT (pin 96) and separate VCCIO rails for each I/O bank (VCCIO1, VCCIO2, VCCIO3). Decouple each VCC rail with a 0.1 µF ceramic capacitor placed as close to the pin as possible, plus a bulk 10 µF tantalum or polymer capacitor on the 3.3 V rail. For MultiVolt operation, each VCCIO rail can be independently set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V to match downstream devices; verify bank assignments in the Quartus pin planner before PCB layout. Pins 37 and 90 MUST be tied to GND; pins 39 and 88 MUST be tied to 3.3 V for the EPM570 die in this package.
Route JTAG signals (TCK, TMS, TDI, TDO) with 50 Ω controlled impedance and keep trace lengths under 50 mm to avoid signal-integrity issues at high programming clock rates. Place the JTAG header or test pad on the board edge for bed-of-nails fixture access. The TQFP-100 footprint has 0.5 mm pitch leads; use a PCB land pattern with at least 0.2 mm solder mask expansion and consider via-in-pad for thermal dissipation. Keep high-speed I/O traces short and impedance-matched to minimize reflections.
Do not confuse the EPM570T100C5N with the EPM240T100C5N - both share the same TQFP-100 package but the EPM240 uses pins 37, 39, 88, 90 as I/O, while on the EPM570 those pins have fixed tie-off requirements (37/90 to GND, 39/88 to 3.3 V). Substituting one for the other without re-routing will result in incorrect JTAG or power behavior. Always verify the device ID readback in Quartus Programmer after programming to confirm the correct silicon is responding.
Compliance Information
RoHS compliant per Altera/Intel product page. Not AEC-Q100 qualified - MAX II CPLDs are not designed for automotive AEC-Q100 applications; consult Intel automotive-grade MAX V or Cyclone families for AEC-Q100 needs.
