EPM7128EQC100-20 - MAX 7000 CPLD, 128 Macrocells, 84 I/O | Altera
N.º da peça: EPM7128EQC100-20 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $14.1 | $1.410,00 |
| 500 | $12.4 | $6.200,00 |
| 1.000 | $11.05 | $11.050,00 |
EPM7128EQC100-20 Visão geral
An EPLD (Erasable Programmable Logic Device) is a non-volatile, electrically erasable CMOS logic device that sits hierarchically between PAL/GAL simple PLDs and full FPGAs. Within the MAX 7000 architecture, logic is organized into Logic Array Blocks (LABs), each containing 16 macrocells with a programmable AND/OR array, a product-term allocator, and a configurable flip-flop. A global Interconnect Array (PIA) routes signals between LABs and the I/O pins, and a JTAG-compliant IEEE 1149.1 boundary-scan interface is provided for in-system programming (ISP) and board-level testing.
Key features of the EPM7128EQC100-20 include 128 macrocells, 250 MHz maximum internal frequency, 4.5 ns propagation delay (per third-party digchip datasheet summary), CMOS 5V I/O with 3.3V/5V tolerant interfacing, in-system programmability via JTAG, and a commercial operating temperature grade of 0°C to 90°C. The 100-pin PQFP package supports 84 user I/Os while providing dedicated JTAG, clock, clear and global OE pins, making it suitable for legacy parallel-bus interfaces, address decoding, and peripheral control logic.
Typical applications include industrial control boards, telecommunications glue logic, address decoding and bus interfacing for legacy microprocessors, peripheral controllers, and pin-compatible upgrades for older MAX 7000 designs. With 128 macrocells the device can absorb the equivalent of roughly 200 to 400 standard 22V10-style PAL equations in a single chip, simplifying board BOMs and reducing chip count in mature designs.
When designing with this part, engineers should note that the 5V core supply, commercial temperature grade and PQFP footprint are characteristic of 1990s-era designs. Modern 3.3V-only or low-power designs should consider MAX II, MAX V or MAX 10 CPLDs as alternatives, as the EPM7128EQC100-20 is now typically sourced for maintenance, repair and legacy production rather than new designs. Designers must observe the 20 ns timing budget carefully for high-speed bus interfaces such as ISA or PCI.
This page synthesizes distributor pricing, drop-in same-package alternatives (EPM7128EQC100-10, EPM7128SQC100-7, EPM7128STC100-10), pinout data and practical design notes not assembled in any single manufacturer document.
Alternativas drop-in para EPM7128EQC100-20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM7128EQC100-20 (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Family, Usable Gates, Device Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM7128EQC100-10
✅ Drop-In✓ Em estoque
$9.85 / unidade
Ver ficha técnica →EPM7128STC100-10
✅ Drop-In✓ Em estoque
$7.1 / unidade
Ver ficha técnica →EPM7128SQC100-7
✅ Drop-In✓ Em estoque
$10.85 / unidade
Ver ficha técnica →EPM7128EQC100-20 Classificações máximas e características elétricas
| Family | MAX 7000 |
| Device Type | EPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Usable Gates | 2.5K |
| User I/Os | 84 |
| Logic Elements / LABs | 8 LABs (16 macrocells per LAB) |
| Propagation Delay (tpd) | 20 ns |
| Maximum Internal Frequency | 250 MHz |
| Technology | CMOS, UV-erasable / EEPROM |
| Tensão de alimentação | 5 V |
| Temperatura de operação | 0 C to 90 C (Commercial) |
| Encapsulamento | 100-pin PQFP (BQFP, gull-wing) |
| Tipo de montagem | Surface Mount |
| In-System Programming | Yes (IEEE 1149.1 JTAG) |
| Compliance | RoHS compliance status not confirmed in web data |
Configuração de pinos do EPM7128EQC100-20
| Pino 1 | I/O — User I/O - macrocell pin 73 |
| Pino 2 | I/O — User I/O - macrocell pin 74 |
| Pino 3 | I/O — User I/O - macrocell pin 75 |
| Pino 4 | I/O — User I/O - macrocell pin 76 |
| Pino 5 | I/O — User I/O - macrocell pin 77 |
| Pino 6 | I/O — User I/O - macrocell pin 78 |
| Pino 7 | I/O — User I/O - macrocell pin 79 |
| Pino 8 | I/O — User I/O - macrocell pin 80 |
| Pino 9 | I/O — User I/O - macrocell pin 81 |
| Pino 10 | I/O — User I/O - macrocell pin 82 |
| Pino 11 | I/O — User I/O - macrocell pin 83 |
| Pino 12 | I/O — User I/O - macrocell pin 84 |
| Pino 13 | GND — Ground |
| Pino 14 | I/O — User I/O - macrocell pin 85 |
| Pino 15 | I/O — User I/O - macrocell pin 86 |
| Pino 16 | I/O — User I/O - macrocell pin 87 |
| Pino 17 | I/O — User I/O - macrocell pin 88 |
| Pino 18 | I/O — User I/O - macrocell pin 89 |
| Pino 19 | I/O — User I/O - macrocell pin 90 |
| Pino 20 | I/O — User I/O - macrocell pin 91 |
| Pino 21 | I/O — User I/O - macrocell pin 92 |
| Pino 22 | I/O — User I/O - macrocell pin 93 |
| Pino 23 | I/O — User I/O - macrocell pin 94 |
| Pino 24 | GND — Ground |
| Pino 25 | I/O — User I/O - macrocell pin 95 |
| Pino 26 | I/O — User I/O - macrocell pin 96 |
| Pino 27 | I/O — User I/O - macrocell pin 97 |
| Pino 28 | I/O — User I/O - macrocell pin 98 |
| Pino 29 | I/O — User I/O - macrocell pin 99 |
| Pino 30 | I/O — User I/O - macrocell pin 100 |
| Pino 31 | I/O — User I/O - macrocell pin 101 |
| Pino 32 | I/O — User I/O - macrocell pin 102 |
| Pino 33 | I/O — User I/O - macrocell pin 103 |
| Pino 34 | I/O — User I/O - macrocell pin 104 |
| Pino 35 | I/O — User I/O - macrocell pin 105 |
| Pino 36 | GND — Ground |
| Pino 37 | I/O — User I/O - macrocell pin 106 |
| Pino 38 | I/O — User I/O - macrocell pin 107 |
| Pino 39 | I/O — User I/O - macrocell pin 108 |
| Pino 40 | I/O — User I/O - macrocell pin 109 |
| Pino 41 | I/O — User I/O - macrocell pin 110 |
| Pino 42 | I/O — User I/O - macrocell pin 111 |
| Pino 43 | I/O — User I/O - macrocell pin 112 |
| Pino 44 | I/O — User I/O - macrocell pin 113 |
| Pino 45 | I/O — User I/O - macrocell pin 114 |
| Pino 46 | I/O — User I/O - macrocell pin 115 |
| Pino 47 | GND — Ground |
| Pino 48 | I/O — User I/O - macrocell pin 116 |
| Pino 49 | I/O — User I/O - macrocell pin 117 |
| Pino 50 | I/O — User I/O - macrocell pin 118 |
| Pino 51 | I/O — User I/O - macrocell pin 119 |
| Pino 52 | I/O — User I/O - macrocell pin 120 |
| Pino 53 | I/O — User I/O - macrocell pin 121 |
| Pino 54 | I/O — User I/O - macrocell pin 122 |
| Pino 55 | I/O — User I/O - macrocell pin 123 |
| Pino 56 | I/O — User I/O - macrocell pin 124 |
| Pino 57 | I/O — User I/O - macrocell pin 125 |
| Pino 58 | I/O — User I/O - macrocell pin 126 |
| Pino 59 | I/O — User I/O - macrocell pin 127 |
| Pino 60 | I/O — User I/O - macrocell pin 128 |
| Pino 61 | GND — Ground |
| Pino 62 | I/O — User I/O - macrocell pin 1 |
| Pino 63 | I/O — User I/O - macrocell pin 2 |
| Pino 64 | I/O — User I/O - macrocell pin 3 |
| Pino 65 | I/O — User I/O - macrocell pin 4 |
| Pino 66 | I/O — User I/O - macrocell pin 5 |
| Pino 67 | I/O — User I/O - macrocell pin 6 |
| Pino 68 | I/O — User I/O - macrocell pin 7 |
| Pino 69 | I/O — User I/O - macrocell pin 8 |
| Pino 70 | I/O — User I/O - macrocell pin 9 |
| Pino 71 | I/O — User I/O - macrocell pin 10 |
| Pino 72 | I/O — User I/O - macrocell pin 11 |
| Pino 73 | I/O — User I/O - macrocell pin 12 |
| Pino 74 | GND — Ground |
| Pino 75 | I/O — User I/O - macrocell pin 13 |
| Pino 76 | I/O — User I/O - macrocell pin 14 |
| Pino 77 | I/O — User I/O - macrocell pin 15 |
| Pino 78 | I/O — User I/O - macrocell pin 16 |
| Pino 79 | I/O — User I/O - macrocell pin 17 |
| Pino 80 | I/O — User I/O - macrocell pin 18 |
| Pino 81 | I/O — User I/O - macrocell pin 19 |
| Pino 82 | I/O — User I/O - macrocell pin 20 |
| Pino 83 | I/O — User I/O - macrocell pin 21 |
| Pino 84 | I/O — User I/O - macrocell pin 22 |
| Pino 85 | I/O — User I/O - macrocell pin 23 |
| Pino 86 | I/O — User I/O - macrocell pin 24 |
| Pino 87 | GND — Ground |
| Pino 88 | I/O — User I/O - macrocell pin 25 |
| Pino 89 | I/O — User I/O - macrocell pin 26 |
| Pino 90 | I/O — User I/O - macrocell pin 27 |
| Pino 91 | I/O — User I/O - macrocell pin 28 |
| Pino 92 | TDI — JTAG Test Data In |
| Pino 93 | TMS — JTAG Test Mode Select |
| Pino 94 | TCK — JTAG Test Clock |
| Pino 95 | TDO — JTAG Test Data Out |
| Pino 96 | GCLK — Global Clock input |
| Pino 97 | OE2 — Global Output Enable 2 |
| Pino 98 | OE1 — Global Output Enable 1 |
| Pino 99 | GCLRn — Global Clear (active low) |
| Pino 100 | VCC — +5 V Supply |
Aplicações típicas
EPM7128EQC100-20 é adequado para 7 aplicaçãos: Legacy ISA / Peripheral Bus Address Decoding, Industrial Control Glue Logic Replacement, Telecommunications Backplane Glue Logic, VME / VXI Bus Interface Controllers, Peripheral and I/O Expansion Controllers, Legacy Microprocessor Address/Data Demultiplexing, Test and Measurement Equipment Front-End Logic.
Legacy ISA / Peripheral Bus Address Decoding
The EPM7128EQC100-20's 128 macrocells and 84 user I/Os are ideal for replacing multiple 22V10-style PAL/GAL devices that decode ISA-bus or legacy peripheral addresses in industrial motherboards. With 20 ns tpd it comfortably meets the ISA 8 MHz bus cycle and even older 16-bit peripheral timings. Place the CPLD between the address bus and chip-select lines, programming each macrocell as a sum-of-products decoder. Compared with discrete PALs, the 128 macrocells consolidate 5-10 address decoders into a single chip, reducing board area and BOM count. Boundary-scan JTAG allows in-system re-programming when address maps change.
Recomendado
Industrial Control Glue Logic Replacement
In PLC backplanes and motor-control boards, the EPM7128EQC100-20 absorbs scattered 74HC/74LS glue logic, custom state machines, and timing generators in a single non-volatile CMOS device. Its 5V I/O directly interfaces with legacy TTL/CMOS logic without level shifters. The 0-90°C commercial temperature grade covers most indoor industrial enclosures, and the PQFP-100 footprint is drop-in compatible with the EPM7128SQC100-7 and EPM7128STC100-10. Engineers designing new boards, however, should consider the MAX II EPM570 or MAX V CPLDs for lower power and smaller footprint, reserving the EPM7128EQC100-20 for legacy maintenance.
Recomendado
Telecommunications Backplane Glue Logic
In telecom backplanes designed in the late 1990s and 2000s, the EPM7128EQC100-20 served as the central glue-logic hub for time-slot assignment, framing, and alarm interfacing. Its 84 I/Os handle multiple parallel buses simultaneously, and JTAG programming enables field firmware updates without removing the board from service. Although modern telecom designs have migrated to FPGAs, the device remains in production spares for legacy systems. For new telecom designs the MAX 10 (10M08) or Cyclone IV are preferred due to lower power and integrated transceivers.
Recomendado
VME / VXI Bus Interface Controllers
VME and VXI instrumentation systems rely on the EPM7128EQC100-20 for bus arbitration, interrupt steering and address decoding. The 20 ns tpd easily satisfies the 16 MHz VMEbus specification, and the 84 user I/Os accommodate the full VME data/address multiplex. Drop-in upgrade to the EPM7128SQC100-7 (7.5 ns) provides margin for VME64 implementations. The device's 5V I/O matches VME's 5V signaling environment directly. Engineers should observe the 100-pin PQFP thermal envelope; convection-cooled VME cards should add a small copper heatsink if operating near 90°C ambient.
Recomendado
Peripheral and I/O Expansion Controllers
The EPM7128EQC100-20 is widely used as a peripheral expansion controller, aggregating parallel I/O for keypads, LCD displays, and stepper-motor drivers in industrial terminals. With 128 macrocells the device can implement a 16-channel multiplexer, an 8-bit counter/timer bank, and a small UART state machine simultaneously, freeing the host CPU from real-time I/O tasks. In-system programmability via JTAG enables field reconfiguration of I/O mappings without board rework. The 5V tolerant inputs interface directly with TTL-level sensors and 5V CMOS peripherals without external buffers.
Recomendado
Legacy Microprocessor Address/Data Demultiplexing
When interfacing 8051, 68HC11, or Z80 microprocessors to external memory and peripherals, the EPM7128EQC100-20 demultiplexes the address/data bus, generates chip selects, and implements wait-state logic. Its 128 macrocells easily handle the full address decode for up to 1 MB memory maps with peripheral selects. The 20 ns tpd is fast enough for 25 MHz 8051-family microcontrollers, and JTAG ISP simplifies firmware iteration. The PQFP-100 footprint suits through-hole adapter boards when adapting legacy designs to surface-mount assembly lines.
Recomendado
Test and Measurement Equipment Front-End Logic
In oscilloscopes, logic analyzers and data-acquisition front-ends, the EPM7128EQC100-20 implements trigger logic, channel gating, and timing generators that require deterministic propagation delay. The 20 ns tpd is sufficiently repeatable for time-interpolation triggers and pattern generators. The 84 I/Os accommodate 16+ parallel channels of trigger logic, and the 5V CMOS core handles TTL/CMOS signal conditioning directly. For new designs, the MAX II EPM570 with 3.3V/2.5V I/O banks and lower dynamic power is recommended, but the EPM7128EQC100-20 remains in service for legacy instrument repair.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM7128EQC100-20 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM7128EQC100-10 | EPM7128STC100-10 | EPM7128SQC100-7 |
|---|---|---|---|---|
| Package | PQFP-100 | PQFP-100 (same) | PQFP-100 (same) | PQFP-100 (same) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX 7000 | MAX 7000 | MAX 7000S | MAX 7000S |
| Macrocells | 128 | 128 | 128 | 128 |
| User I/Os | 84 | 84 | 84 | 84 |
| Propagation Delay (tpd) | 20 ns | 10 ns | 10 ns | 7.5 ns |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0 C to 90 C (Commercial) | 0 C to 90 C | 0 C to 90 C | 0 C to 90 C |
| In-System Programming | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Speed Grade Improvement | Baseline | 50% faster | 50% faster | 62% faster |
Principais diferenciais
- Industry-standard MAX 7000 architecture with 128 macrocells in PQFP-100 (vs EPM7064QC100-1)
- 5V CMOS I/O directly compatible with legacy TTL logic (vs MAX II EPM570T100C5N)
- Pin-compatible with multiple MAX 7000 speed grades for upgrade paths (vs EPM7128ELC84-20)
Notas de projeto
The EPM7128EQC100-20 requires a stable 5V supply on pin 100 (VCC) with decoupling capacitors placed within 5 mm of every VCC pin and multiple ground pins (13, 24, 36, 47, 61, 74, 87). Use a 100 nF ceramic per supply pin plus a single 10 uF tantalum bulk capacitor at the board entry point. The MAX 7000 family draws up to 300 mA during programming pulses via JTAG, so the supply must source this transient without sagging below 4.75 V.
For the 100-pin PQFP package, allocate at least 1.5x the package body width as a keep-out area around the chip for probe access during JTAG ISP programming. Route all JTAG signals (TDI/TDO/TMS/TCK) on a dedicated layer with 50 ohm characteristic impedance and a 10 kohm pull-up on TCK and TMS. Avoid routing high-speed signals under the PQFP body to prevent crosstalk into the 84 user I/Os. The PQFP gull-wing leads require 0.25 mm minimum clearance for inspection.
The MAX 7000 I/O structure supports 5V CMOS levels directly. When interfacing with 3.3V peripherals, use the EPM7128EQC100-20 as a 5V driver with 3.3V-compatible inputs (the inputs are 5V tolerant even when VCCIO is 5V). For clock signals, keep trace lengths matched within 5 mm across the GCLK pin and avoid stub branches. The 20 ns tpd budget translates to roughly 50 MHz maximum toggle frequency on a single macrocell; designs requiring faster edges should target the SQC100-7 variant.
Do not assume any MAX 7000 device in PQFP-100 is bitstream-compatible with the EPM7128EQC100-20: while pin-compatible mechanically, the SQC100-7 and STC100-10 have different JTAG IDs and require recompilation of the Quartus/MAX+PLUS II program object file. Always re-run timing analysis after a speed-grade swap. Also note that the MAX 7000 EEPROM programming model requires a 12V VPP for older UV-erasable variants, but the EPM7128EQC100-20 is in-system programmable via JTAG at 5V only.
Estimated: at 100% I/O toggling at 25 MHz with 50 pF loads, the EPM7128EQC100-20 dissipates approximately 0.6-0.9 W. With theta_JA of approximately 50 C/W for the PQFP-100 package (no heatsink), junction temperature rises 30-45 C above ambient. In a sealed enclosure at 70 C ambient the junction could reach 100-115 C, well below the 150 C maximum. For continuous high-toggle designs, add a small copper heatsink or forced-air cooling to keep Tj below 100 C.
Informações de conformidade
Compliance status not explicitly stated in the verified web data. The EPM7128EQC100-20 is a 1990s-era product from Altera; RoHS-compliant variants are typically marked with an 'N' suffix (e.g., EPM7128EQC100-20N) but were not confirmed in the provided data.
