EPM9560RI208-15 - 560-Macrocell MAX 9000 CPLD, 208-Pin RQFP | Intel
Артикул: EPM9560RI208-15 ✗ Снят с производства| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $33.2 | $332,00 |
| 100 | $27.8 | $2.780,00 |
| 500 | $23.45 | $11.725,00 |
| 1.000 | $20.1 | $20.100,00 |
EPM9560RI208-15 Обзор
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like logic blocks on a single die with a global interconnect matrix. In the system hierarchy, CPLDs sit between simple SPLDs (PAL/GAL) and FPGAs: they offer deterministic, tCO-class timing, instant-on configuration from on-chip EEPROM, and high-drive I/O suited to bus-interface and glue-logic roles. The MAX 9000 family extends the classic MAX architecture to densities between 5,000 and 12,000 usable gates, positioning the EPM9560 as the mid-to-high density member with 12,000 typical gates.
Key features of the EPM9560RI208-15 include in-system programmability (ISP) via JTAG (IEEE 1149.1), 5.0 V VCCIO-tolerant multi-volt I/O (3.3 V or 5 V mixed-mode), 16 macrocell LABs of 16 macrocells each, four global clock pins, programmable power-saving per macrocell, and JTAG boundary-scan testability. The 208-pin RQFP gull-wing package gives a thermal resistance suitable for 0 to 70 °C commercial environments in the -15 speed grade.
The architecture uses a high-performance CMOS EEPROM process, providing non-volatile configuration retention, fast in-system erase/program, and predictable combinational/sequential logic. The interconnect is a continuous, fast-path Programmable Interconnect Array (PIA) that routes any LAB output to any other LAB input without contention, simplifying timing closure for control and bus-interface designs.
Typical applications include bus-interface glue logic (PCI bridges, address decoding), 5 V to 3.3 V level shifting, microcontroller peripheral expansion, state-machine controllers, JTAG-based boundary-scan boards, and industrial control glue where instant-on, non-volatile boot is required. With 153 user I/Os in a 208-pin footprint, the EPM9560 is well matched to wide-bus interface designs.
When designing with this device, observe the 5 V nominal supply tolerance (typically 4.5 V to 5.5 V), provide adequate decoupling (0.1 µF per VCC pin plus bulk), and follow Altera MAX 9000 JTAG ISP guidelines for in-system programming. The MAX+PLUS II or Quartus II toolchain (legacy) is required for design entry, fitting, and verification.
This page synthesizes distributor pricing, EPM9560 family cross-references, drop-in pin-compatible same-brand alternatives (EPM9560 family speed/package variants), and practical design notes not consolidated in any single manufacturer document.
Аналоги без доработки для EPM9560RI208-15 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с EPM9560RI208-15 (тот же форм-фактор и посадочное место) — отличается по Package, Operating Temperature, In-System Programmability, Device Type, Architecture.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
EPM9560RI208-10
✅ Прямая замена✓ В наличии
$67.8 / шт.
Открыть даташит →EPM9560RI208-10N
✅ Прямая замена✓ В наличии
$61.75 / шт.
Открыть даташит →EPM9560RI208-20
✅ Прямая замена✓ В наличии
$21.1 / шт.
Открыть даташит →EPM9560RC208-15
✅ Прямая замена ⚠️ Характеристики не проверены✓ В наличии
Уточнить цену
Открыть даташит →EPM9560RC208-10
✅ Прямая замена ⚠️ Характеристики не проверены✓ В наличии
$15.4 / шт.
Открыть даташит →EPM9560RC208-20
✅ Прямая замена ⚠️ Характеристики не проверены✓ В наличии
Уточнить цену
Открыть даташит →EPM9560RI208-15 Максимальные параметры и электрические характеристики
| Family | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macrocells | 560 |
| Typical Usable Gates | 12,000 |
| User I/Os | 153 |
| Internal Frequency (max) | 145 MHz |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade |
| Logic Family | CMOS |
| Количество выводов | 208 |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) |
| Package Type | RQFP-208 |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O |
| Рабочая температура | 0 °C to 70 °C (industrial grade; per package suffix R) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) |
| Boundary-Scan (JTAG) | Compliant |
| Configuration Memory | On-chip EEPROM (non-volatile) |
| Статус RoHS | ROHS3 Compliant |
| Уровень чувствительности к влаге (MSL) | 3 (168 hours) |
Руководство по цоколевке EPM9560RI208-15 в корпусе rqfp-208
Цоколевка для EPM9560RI208-15 (корпус rqfp-208). Эта цифровая ИС включает выводы GPIO, интерфейсы связи (UART, SPI, I2C) и выводы питания. Обратитесь к техническому описанию производителя для альтернативных функций выводов и вариантов конфигурации. Необходимо для проектирования встраиваемых систем и трассировки печатных плат.
Нет подробных данных о распиновке для EPM9560RI208-15.
Обратитесь к даташиту для полной конфигурации выводов.
Типичное применение
EPM9560RI208-15 подходит для 6 применениеs: PCI Bus Interface & Address Decoding, 5 V to 3.3 V Level Shifting & Mixed-Voltage Glue Logic, Industrial Control Glue Logic & State-Machine Controllers, Microcontroller Peripheral Expansion, JTAG-Based Boundary-Scan Board Testing, Legacy Industrial Replacement & Long-Life Systems.
PCI Bus Interface & Address Decoding
The EPM9560RI208-15's 560 macrocells, 153 user I/Os, and deterministic 15 ns tPD make it ideal for PCI bridge, address-decoding, and wait-state generation in legacy bus-interface designs. With 5 V tolerant multi-volt I/O it directly interfaces PCI 5 V signaling, while JTAG ISP enables post-assembly board reprogramming for prototype iterations. The fast PIA interconnect routes any LAB output to any LAB input without contention, simplifying timing closure for combinational decode paths. Used between a host CPU and peripheral bus to assert chip selects, generate cycle timing, and arbitrate interrupts - all in a single non-volatile device. Compared to a discrete PAL/GAL solution, the EPM9560RI208-15 consolidates an entire decode-PAL farm into one chip.
Рекомендуется
5 V to 3.3 V Level Shifting & Mixed-Voltage Glue Logic
The EPM9560RI208-15's multi-volt I/O (3.3 V or 5 V per pin) and 5 V VCC supply make it a natural choice for bridging 5 V legacy ASICs to 3.3 V microcontrollers, ASICs, and memories. Each macrocell can be configured as 3.3 V while the core runs at 5 V, eliminating external level shifter ICs. With 153 user I/Os, a single EPM9560 can translate an entire wide-bus interface - data, address, and control - between two voltage domains. The 15 ns tPD adds <2 ns of timing skew per translator stage, preserving bus timing margin. Designers benefit from instant-on non-volatile configuration, so the device wakes up in the correct state on power-up without external boot memory.
Рекомендуется
Industrial Control Glue Logic & State-Machine Controllers
The EPM9560RI208-15's deterministic timing, instant-on non-volatile EEPROM configuration, and 153 I/Os make it ideal for industrial PLC I/O expansion, motor-control state machines, and sensor-fusion glue logic. Industrial 0-70 °C operating range supports factory-floor enclosures. Its 560 macrocells can implement multiple parallel state machines - one for each axis of a stepper/servo controller, plus safety interlocks and watchdog logic - all in one device. JTAG boundary-scan enables board-level testing of all 153 I/Os in production. Compared to discrete 74HC logic, the EPM9560 reduces board area by 5-10x and lets engineers modify state-machine behavior late in the design cycle.
Рекомендуется
Microcontroller Peripheral Expansion
The EPM9560RI208-15 expands microcontroller I/O and offloads timing-critical tasks in 8/16/32-bit MCU designs where the MCU pin count or peripheral set is insufficient. Designers route UART, SPI, PWM, capture, and GPIO expansion through the CPLD's 153 I/Os while the MCU focuses on application code. The 15 ns tPD supports real-time peripheral multiplexing and interrupt prioritization without CPU intervention. With EEPROM-based configuration, the expansion personality is fixed at board power-up - no firmware boot loader required. Compared to an I/O expander ASIC, the EPM9560RI208-15 is software-reprogrammable, enabling late-stage design changes and field firmware updates via JTAG.
Рекомендуется
JTAG-Based Boundary-Scan Board Testing
The EPM9560RI208-15's full IEEE 1149.1 JTAG compliance and 153 user I/Os make it a workhorse for boundary-scan testability in complex multi-board systems. Each I/O pin can be observed or driven through the JTAG TAP, enabling interconnect testing between boards without bed-of-nails fixtures. With 560 macrocells available, the device can also implement board-test logic (BIST, scan chains, ID loops) alongside its operational function. Compared to a discrete JTAG controller ASIC, the EPM9560RI208-15 combines operational logic and test infrastructure in one reprogrammable part, reducing BOM and accelerating board bring-up.
Рекомендуется
Legacy Industrial Replacement & Long-Life Systems
The EPM9560RI208-15 is often specified in long-life industrial, medical, and aerospace systems where the original MAX 9000 design has been in production for 15-20+ years. Industrial 0-70 °C operating range and EEPROM non-volatile configuration support field-deployed equipment that must boot deterministically without firmware updates. Engineers replacing EOL boards use the EPM9560RI208-15 as a pin-compatible, footprint-identical substitute for the original MAX 9000 part. Compared to migrating to MAX II / MAX V (which requires PCB redesign, toolchain migration, and re-qualification), keeping the EPM9560RI208-15 in production saves months of re-validation work.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для EPM9560RI208-15 — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | EPM9560RI208-10 | EPM9560RI208-10N | EPM9560RI208-20 | EPM9560RC208-15 | EPM9560RC208-10 | EPM9560RC208-20 |
|---|---|---|---|---|---|---|---|
| Package | RQFP-208 (industrial) | RQFP-208 (industrial) | RQFP-208 (industrial) | RQFP-208 (industrial) | PQFP-208 | PQFP-208 | PQFP-208 |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| User I/Os | 153 | 153 | 153 | 153 | 153 | 153 | 153 |
| Propagation Delay (tPD) | 15 ns | 10 ns (faster) | 10 ns (faster) | 20 ns (slower) | 15 ns | 10 ns (faster) | 20 ns (slower) |
| Internal Frequency (max) | 145 MHz | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) |
| Supply Voltage | 5 V (4.5 V to 5.5 V) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Pin-to-Pin Compatibility | Reference | Yes (drop-in) | Yes (drop-in) | Yes (drop-in) | Yes (verify land pattern) | Yes (verify land pattern) | Yes (verify land pattern) |
Ключевые отличия
- Highest I/O count in the MAX 9000 RQFP-208 family (против EPM9320RI208-20)
- Non-volatile EEPROM configuration enables instant-on (против MAX II EPM1270 (SRAM-based))
- Industrial temperature grade in RQFP package (против EPM9560RC208-15 (PQFP commercial))
Заметки по проектированию
Estimated: at 145 MHz internal frequency with 50% macrocell utilization, the EPM9560RI208-15 draws approximately 300-500 mA from a 5 V supply, with peaks up to 700 mA during simultaneous switching of all 153 I/Os. Provide at least 4x 0.1 µF ceramic decoupling capacitors (one per VCC pin group) plus a 47-100 µF bulk capacitor at the board 5 V rail. Place the bulk capacitor within 25 mm of the device. Designers should also include a 0.1 µF cap on each VCCIO bank to limit switching-noise-induced VCCIO bounce.
The 208-pin RQFP (Power Quad Flat Pack) has a 0.5 mm lead pitch and ~30 mm body. Place the device on the top side of the PCB with continuous ground plane on layer 2 and a 5 V power plane on layer 3 directly under the device. Route all 153 user I/O signals on the top layer with short stubs to vias on inner signal layers; keep clock and JTAG traces length-matched to within 5 mm. Provide a 4-layer PCB minimum (signal-GND-power-signal) for noise isolation; 2-layer PCBs are unsuitable above 50 MHz internal frequencies.
Do not assume the EPM9560RI208-15 has 5 V tolerance on its JTAG pins - check the MAX 9000 datasheet for VCCIO requirements on TCK/TMS/TDI/TDO/TRST. Also note that the -15 speed grade (15 ns tPD) is the slowest currently shipping for the 208-pin RQFP; if timing closure is not achievable, migrate to the -10 speed grade. Do not exceed 5.5 V VCC; transient overvoltage can permanently damage the EEPROM cells. Finally, do not program the device with a JTAG chain that includes 3.3 V-only devices unless you use a level shifter in the chain - mixed-voltage JTAG chains require level translation.
Информация о соответствии
ROHS3 Compliant per fpgalink.com listing. MSL-3 (168 hours) moisture sensitivity requires dry-pack handling and bake-out before reflow. Not AEC-Q100 qualified (industrial temperature grade, not automotive).
