EPM9560RI208-15 - 560-Macrocell MAX 9000 CPLD, 208-Pin RQFP | Intel
MPN: EPM9560RI208-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $27.8 | $2,780.00 |
| 500 | $23.45 | $11,725.00 |
| 1,000 | $20.1 | $20,100.00 |
Drop-in alternatives for EPM9560RI208-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RI208-10
✅ Drop-In✓ In Stock
$67.8 / Unit
View Datasheet →EPM9560RI208-10N
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$61.75 / Unit
View Datasheet →EPM9560RI208-20
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$21.1 / Unit
View Datasheet →EPM9560RC208-15
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View Datasheet →EPM9560RC208-10
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$15.4 / Unit
View Datasheet →EPM9560RC208-20
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View Datasheet →EPM9560RI208-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macrocells | 560 |
| Typical Usable Gates | 12,000 |
| User I/Os | 153 |
| Internal Frequency (max) | 145 MHz |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade |
| Logic Family | CMOS |
| Number of Pins | 208 |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) |
| Package Type | RQFP-208 |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O |
| Operating Temperature | 0 °C to 70 °C (industrial grade; per package suffix R) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) |
| Boundary-Scan (JTAG) | Compliant |
| Configuration Memory | On-chip EEPROM (non-volatile) |
| RoHS Status | ROHS3 Compliant |
| Moisture Sensitivity Level (MSL) | 3 (168 hours) |
EPM9560RI208-15 rqfp-208 Pin Configuration Guide
Complete pinout information for EPM9560RI208-15 (rqfp-208 package) with 208 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RI208-15.
Refer to the datasheet for full pin configuration.
Estimated pin count: 208 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI208-15 is suitable for 6 applications: PCI Bus Interface & Address Decoding, 5 V to 3.3 V Level Shifting & Mixed-Voltage Glue Logic, Industrial Control Glue Logic & State-Machine Controllers, Microcontroller Peripheral Expansion, JTAG-Based Boundary-Scan Board Testing, Legacy Industrial Replacement & Long-Life Systems.
PCI Bus Interface & Address Decoding
The EPM9560RI208-15's 560 macrocells, 153 user I/Os, and deterministic 15 ns tPD make it ideal for PCI bridge, address-decoding, and wait-state generation in legacy bus-interface designs. With 5 V tolerant multi-volt I/O it directly interfaces PCI 5 V signaling, while JTAG ISP enables post-assembly board reprogramming for prototype iterations. The fast PIA interconnect routes any LAB output to any LAB input without contention, simplifying timing closure for combinational decode paths. Used between a host CPU and peripheral bus to assert chip selects, generate cycle timing, and arbitrate interrupts - all in a single non-volatile device. Compared to a discrete PAL/GAL solution, the EPM9560RI208-15 consolidates an entire decode-PAL farm into one chip.
Recommended
5 V to 3.3 V Level Shifting & Mixed-Voltage Glue Logic
The EPM9560RI208-15's multi-volt I/O (3.3 V or 5 V per pin) and 5 V VCC supply make it a natural choice for bridging 5 V legacy ASICs to 3.3 V microcontrollers, ASICs, and memories. Each macrocell can be configured as 3.3 V while the core runs at 5 V, eliminating external level shifter ICs. With 153 user I/Os, a single EPM9560 can translate an entire wide-bus interface - data, address, and control - between two voltage domains. The 15 ns tPD adds <2 ns of timing skew per translator stage, preserving bus timing margin. Designers benefit from instant-on non-volatile configuration, so the device wakes up in the correct state on power-up without external boot memory.
Recommended
Industrial Control Glue Logic & State-Machine Controllers
The EPM9560RI208-15's deterministic timing, instant-on non-volatile EEPROM configuration, and 153 I/Os make it ideal for industrial PLC I/O expansion, motor-control state machines, and sensor-fusion glue logic. Industrial 0-70 °C operating range supports factory-floor enclosures. Its 560 macrocells can implement multiple parallel state machines - one for each axis of a stepper/servo controller, plus safety interlocks and watchdog logic - all in one device. JTAG boundary-scan enables board-level testing of all 153 I/Os in production. Compared to discrete 74HC logic, the EPM9560 reduces board area by 5-10x and lets engineers modify state-machine behavior late in the design cycle.
Recommended
Microcontroller Peripheral Expansion
The EPM9560RI208-15 expands microcontroller I/O and offloads timing-critical tasks in 8/16/32-bit MCU designs where the MCU pin count or peripheral set is insufficient. Designers route UART, SPI, PWM, capture, and GPIO expansion through the CPLD's 153 I/Os while the MCU focuses on application code. The 15 ns tPD supports real-time peripheral multiplexing and interrupt prioritization without CPU intervention. With EEPROM-based configuration, the expansion personality is fixed at board power-up - no firmware boot loader required. Compared to an I/O expander ASIC, the EPM9560RI208-15 is software-reprogrammable, enabling late-stage design changes and field firmware updates via JTAG.
Recommended
JTAG-Based Boundary-Scan Board Testing
The EPM9560RI208-15's full IEEE 1149.1 JTAG compliance and 153 user I/Os make it a workhorse for boundary-scan testability in complex multi-board systems. Each I/O pin can be observed or driven through the JTAG TAP, enabling interconnect testing between boards without bed-of-nails fixtures. With 560 macrocells available, the device can also implement board-test logic (BIST, scan chains, ID loops) alongside its operational function. Compared to a discrete JTAG controller ASIC, the EPM9560RI208-15 combines operational logic and test infrastructure in one reprogrammable part, reducing BOM and accelerating board bring-up.
Recommended
Legacy Industrial Replacement & Long-Life Systems
The EPM9560RI208-15 is often specified in long-life industrial, medical, and aerospace systems where the original MAX 9000 design has been in production for 15-20+ years. Industrial 0-70 °C operating range and EEPROM non-volatile configuration support field-deployed equipment that must boot deterministically without firmware updates. Engineers replacing EOL boards use the EPM9560RI208-15 as a pin-compatible, footprint-identical substitute for the original MAX 9000 part. Compared to migrating to MAX II / MAX V (which requires PCB redesign, toolchain migration, and re-qualification), keeping the EPM9560RI208-15 in production saves months of re-validation work.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI208-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI208-10 | EPM9560RI208-10N | EPM9560RI208-20 | EPM9560RC208-15 | EPM9560RC208-10 | EPM9560RC208-20 |
|---|---|---|---|---|---|---|---|
| Package | RQFP-208 (industrial) | RQFP-208 (industrial) | RQFP-208 (industrial) | RQFP-208 (industrial) | PQFP-208 | PQFP-208 | PQFP-208 |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| User I/Os | 153 | 153 | 153 | 153 | 153 | 153 | 153 |
| Propagation Delay (tPD) | 15 ns | 10 ns (faster) | 10 ns (faster) | 20 ns (slower) | 15 ns | 10 ns (faster) | 20 ns (slower) |
| Internal Frequency (max) | 145 MHz | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) | 145 MHz (same) |
| Supply Voltage | 5 V (4.5 V to 5.5 V) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Pin-to-Pin Compatibility | Reference | Yes (drop-in) | Yes (drop-in) | Yes (drop-in) | Yes (verify land pattern) | Yes (verify land pattern) | Yes (verify land pattern) |
Key Differentiators
- Highest I/O count in the MAX 9000 RQFP-208 family (vs EPM9320RI208-20)
- Non-volatile EEPROM configuration enables instant-on (vs MAX II EPM1270 (SRAM-based))
- Industrial temperature grade in RQFP package (vs EPM9560RC208-15 (PQFP commercial))
Design Notes
Estimated: at 145 MHz internal frequency with 50% macrocell utilization, the EPM9560RI208-15 draws approximately 300-500 mA from a 5 V supply, with peaks up to 700 mA during simultaneous switching of all 153 I/Os. Provide at least 4x 0.1 µF ceramic decoupling capacitors (one per VCC pin group) plus a 47-100 µF bulk capacitor at the board 5 V rail. Place the bulk capacitor within 25 mm of the device. Designers should also include a 0.1 µF cap on each VCCIO bank to limit switching-noise-induced VCCIO bounce.
The 208-pin RQFP (Power Quad Flat Pack) has a 0.5 mm lead pitch and ~30 mm body. Place the device on the top side of the PCB with continuous ground plane on layer 2 and a 5 V power plane on layer 3 directly under the device. Route all 153 user I/O signals on the top layer with short stubs to vias on inner signal layers; keep clock and JTAG traces length-matched to within 5 mm. Provide a 4-layer PCB minimum (signal-GND-power-signal) for noise isolation; 2-layer PCBs are unsuitable above 50 MHz internal frequencies.
Do not assume the EPM9560RI208-15 has 5 V tolerance on its JTAG pins - check the MAX 9000 datasheet for VCCIO requirements on TCK/TMS/TDI/TDO/TRST. Also note that the -15 speed grade (15 ns tPD) is the slowest currently shipping for the 208-pin RQFP; if timing closure is not achievable, migrate to the -10 speed grade. Do not exceed 5.5 V VCC; transient overvoltage can permanently damage the EEPROM cells. Finally, do not program the device with a JTAG chain that includes 3.3 V-only devices unless you use a level shifter in the chain - mixed-voltage JTAG chains require level translation.
Compliance Information
ROHS3 Compliant per fpgalink.com listing. MSL-3 (168 hours) moisture sensitivity requires dry-pack handling and bake-out before reflow. Not AEC-Q100 qualified (industrial temperature grade, not automotive).
