Altera

EPM9560RZ208-15 - MAX 9000 EPLD, 560 Logic Elements | Altera

Артикул: EPM9560RZ208-15 ✗ Снят с производства
В наличии Отправка в течение 1–3 рабочих дней
5.0 V Vdss RQFP-208 (PowerQuad QFP) Package -15 (15 ns pin-to-pin delay) Speed
От $55 USD / шт.
MOQ: 1 |
Цена обновлена: 2026-09-13
Оптовые цены
Кол-во Цена за ед. Итого
1 $85 $85,00
10 $76.5 $765,00
100 $68 $6.800,00
500 $61.2 $30.600,00
1.000 $55 $55.000,00
ℹ️ Все цены указаны в USD

EPM9560RZ208-15 Обзор

The Altera (Intel) EPM9560RZ208-15 is a member of the MAX 9000 EPLD family, providing 560 macrocells (approximately 12,000 usable gates) in a 208-pin PowerQuad QFP (RQFP) package with -15 speed grade (15 ns pin-to-pin delay). It is built on a 0.35 µm CMOS EEPROM process that delivers non-volatile, in-system programmable logic for high-density glue-logic, bus-interface, and state-machine consolidation designs.

An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with multi-macrocell arrays, in-system programmability via IEEE 1149.1 JTAG, and predictable timing. In the broader taxonomy, an EPLD is a sub-class of CPLD (Complex Programmable Logic Device), which itself sits between discrete PLDs and high-density FPGAs. MAX 9000 sits near the upper end of the CPLD density envelope offered in the late-1990s/early-2000s Altera portfolio, providing high I/O counts and predictable timing suitable for board-level glue logic.

Key features include 560 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, 5V tolerant I/O on selected variants, in-system programmability (ISP) through JTAG, and a maximum toggle frequency of 100 MHz. The FastTrack interconnect provides continuous routing that yields fully deterministic, hazard-free timing — every path through the device has a guaranteed propagation delay independent of logic placement. Designers can therefore budget timing without floorplanning iterations.

The RQFP-208 package offers 208 pins with low profile suitable for socketed and surface-mount designs. With 212 user I/Os available in the package and high-drive capability on outputs, the EPM9560RZ208-15 is well suited for parallel bus interfaces, address decoding, memory control, and peripheral multiplexing tasks where multiple discrete 74-series devices would otherwise be required. The -15 speed grade delivers tPD = 15 ns, suiting 33 MHz synchronous designs.

Typical applications include legacy industrial control systems, telecommunications backplane glue logic, ISA/PCI bus address decoding, and microcontroller peripheral expansion. The wide I/O count and predictable timing also suit it for ASIC prototyping in designs that later migrate to structured ASIC or gate-array devices.

When designing with the EPM9560RZ208-15, note that the device is a mature part approaching end-of-life. Designers of new products should consider the Altera (Intel) MAX V, MAX II, or MAX 10 CPLD families, which offer lower power, smaller packages, and modern I/O standards. For legacy board replacement, verify pin compatibility with the original design footprint and review the datasheet's DC characteristics, particularly VCCIO banks and 5V tolerance.

This page synthesizes distributor pricing, drop-in alternatives from the MAX 9000 family, and practical design notes not consolidated in the manufacturer datasheet — giving sourcing engineers a single reference for both qualification and substitution decisions.

Аналоги без доработки для EPM9560RZ208-15 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM9560RZ208-15 (тот же форм-фактор и посадочное место) — отличается по Package, Usable Gates, Architecture, Device Type, Configuration Memory.

Altera
Package: 208-pin RQFP (28x28 mm)
Usable Gates: 8,000
Сравнить с EPM9560RZ208-15 →
Intel
Package: RQFP-208
Usable Gates: 10,000 gates
Architecture: Multiple Array MatriX (MAX) - 3rd generation
Сравнить с EPM9560RZ208-15 →
Altera
Package: 208-pin RQFP (Power Quad Flat Pack)
Usable Gates: 12,000 gates
Architecture: Third-generation Multiple Array MatriX (MAX)
Сравнить с EPM9560RZ208-15 →
Intel
Package: 208-pin RQFP (Power Quad Flat Pack)
Device Type: CPLD (Complex Programmable Logic Device)
Configuration Memory: EEPROM, 100 erase/program cycles
Сравнить с EPM9560RZ208-15 →
Intel
Architecture: CMOS EEPROM-based Multiple Array MatriX (MAX)
Configuration Memory: On-chip EEPROM (non-volatile)
Сравнить с EPM9560RZ208-15 →
Intel
Package: 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm
Architecture: Multiple Array MatriX (MAX) - third generation
Device Type: CPLD (Complex Programmable Logic Device)
Сравнить с EPM9560RZ208-15 →

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

EPM9560RI208-15

✅ Прямая замена
Intel
📦 RQFP-208
MAX 9000 · CMOS EEPROM-based Multiple Array MatriX (MAX) · 560 · 12,000 · 153 · 145 MHz · 11.4 ns (commercial); 15 ns speed grade · CMOS

✓ В наличии

$20.1 / шт.

Открыть даташит →

EPM9560RI208-20

✅ Прямая замена
Intel
📦 RQFP-208
MAX 9000 · CPLD (Complex Programmable Logic Device) · Multiple Array MatriX (MAX) - third generation · 12,000 · 560 · 16 · 212 · 20 ns

✓ В наличии

$21.1 / шт.

Открыть даташит →

EPM9560RI208-10

✅ Прямая замена
Intel
📦 RQFP-208
MAX 9000 · CPLD (Complex Programmable Logic Device) · 12,000 · 560 · 10 ns · 144 MHz · 5.0 V

✓ В наличии

$67.8 / шт.

Открыть даташит →

EPM9560RC208-15

✅ Прямая замена
Altera
📦 QFP-208
MAX 9000 · EEPROM-based Complex Programmable Logic Device (CPLD) · 12,000 gates · 560 macro cells · 15 ns · 117.6 MHz · 5.0 V · EEPROM (non-volatile)

✓ В наличии

Уточнить цену

Открыть даташит →

EPM9480RC208-15

✅ Прямая замена
Intel
📦 QFP-208
MAX 9000 · 480 macro cells · 10,000 gates · 117.6 MHz · 15 ns · 153 · 5.0 V · In-System (ISP) via JTAG IEEE 1149.1

✓ В наличии

$24.95 / шт.

Открыть даташит →

EPM9400RC208-20

✅ Прямая замена
Altera
📦 QFP-208
MAX 9000 · In System Programmable (ISP) · 400 · 8,000 · 20 ns · 100 MHz · 4.75 V to 5.25 V · EEPROM-based (non-volatile)

✓ В наличии

$60.49 / шт.

Открыть даташит →

EPM9560RZ208-15 Максимальные параметры и электрические характеристики

Family MAX 9000
Device Type EPLD (Erasable Programmable Logic Device)
Macrocells 560
Usable Gates 12,000
Logic Array Blocks (LABs) 16
User I/O Pins (max) 212
Корпус RQFP-208 (PowerQuad QFP)
Speed Grade -15 (15 ns pin-to-pin delay)
Process Technology 0.35 µm CMOS EEPROM
Operating Voltage (Core) 5.0 V
Programmability In-System Programmable (ISP) via JTAG
Pin-to-Pin Delay (tPD) 15 ns
Тип монтажа Surface Mount

Конфигурация выводов EPM9560RZ208-15

QFP-208 Package Pinout Diagram QFP-208 28x28mm, P0.5mm, JEDEC. 1 52 QFP-208
Контакт 1 GND — Ground reference (TQFP convention - check datasheet for exact assignment)
Контакт 2 I/O — User I/O pin (function assigned by Quartus design)
Контакт 3 I/O — User I/O pin
Контакт 4 I/O — User I/O pin
Контакт 5 I/O — User I/O pin
Контакт 6 I/O — User I/O pin
Контакт 7 I/O — User I/O pin
Контакт 8 I/O — User I/O pin
Контакт 9 I/O — User I/O pin
Контакт 10 I/O — User I/O pin
Контакт 11 I/O — User I/O pin
Контакт 12 I/O — User I/O pin
Контакт 13 I/O — User I/O pin
Контакт 14 I/O — User I/O pin
Контакт 15 I/O — User I/O pin
Контакт 16 GND — Ground reference
Контакт 17 I/O — User I/O pin
Контакт 18 I/O — User I/O pin
Контакт 19 I/O — User I/O pin
Контакт 20 I/O — User I/O pin
Контакт 21 I/O — User I/O pin
Контакт 22 I/O — User I/O pin
Контакт 23 I/O — User I/O pin
Контакт 24 I/O — User I/O pin
Контакт 25 I/O — User I/O pin
Контакт 26 I/O — User I/O pin
Контакт 27 I/O — User I/O pin
Контакт 28 VCC — +5V core supply
Контакт 29 I/O — User I/O pin
Контакт 30 I/O — User I/O pin
Контакт 31 I/O — User I/O pin
Контакт 32 I/O — User I/O pin
Контакт 33 I/O — User I/O pin
Контакт 34 I/O — User I/O pin
Контакт 35 I/O — User I/O pin
Контакт 36 I/O — User I/O pin
Контакт 37 I/O — User I/O pin
Контакт 38 I/O — User I/O pin
Контакт 39 I/O — User I/O pin
Контакт 40 I/O — User I/O pin
Контакт 41 I/O — User I/O pin
Контакт 42 I/O — User I/O pin
Контакт 43 I/O — User I/O pin
Контакт 44 I/O — User I/O pin
Контакт 45 I/O — User I/O pin
Контакт 46 I/O — User I/O pin
Контакт 47 I/O — User I/O pin
Контакт 48 I/O — User I/O pin
Контакт 49 I/O — User I/O pin
Контакт 50 I/O — User I/O pin
Контакт 51 I/O — User I/O pin
Контакт 52 GND — Ground reference
Контакт 53 I/O — User I/O pin
Контакт 54 I/O — User I/O pin
Контакт 55 I/O — User I/O pin
Контакт 56 I/O — User I/O pin
Контакт 57 I/O — User I/O pin
Контакт 58 I/O — User I/O pin
Контакт 59 I/O — User I/O pin
Контакт 60 I/O — User I/O pin
Контакт 61 I/O — User I/O pin
Контакт 62 I/O — User I/O pin
Контакт 63 I/O — User I/O pin
Контакт 64 I/O — User I/O pin
Контакт 65 I/O — User I/O pin
Контакт 66 I/O — User I/O pin
Контакт 67 I/O — User I/O pin
Контакт 68 I/O — User I/O pin
Контакт 69 I/O — User I/O pin
Контакт 70 I/O — User I/O pin
Контакт 71 I/O — User I/O pin
Контакт 72 I/O — User I/O pin
Контакт 73 I/O — User I/O pin
Контакт 74 I/O — User I/O pin
Контакт 75 I/O — User I/O pin
Контакт 76 I/O — User I/O pin
Контакт 77 TDI — JTAG Test Data In
Контакт 78 TMS — JTAG Test Mode Select
Контакт 79 TCK — JTAG Test Clock
Контакт 80 TDO — JTAG Test Data Out
Контакт 81 I/O — User I/O pin
Контакт 82 I/O — User I/O pin
Контакт 83 I/O — User I/O pin
Контакт 84 I/O — User I/O pin
Контакт 85 I/O — User I/O pin
Контакт 86 I/O — User I/O pin
Контакт 87 I/O — User I/O pin
Контакт 88 GND — Ground reference
Контакт 89 I/O — User I/O pin
Контакт 90 I/O — User I/O pin
Контакт 91 I/O — User I/O pin
Контакт 92 I/O — User I/O pin
Контакт 93 I/O — User I/O pin
Контакт 94 I/O — User I/O pin
Контакт 95 I/O — User I/O pin
Контакт 96 I/O — User I/O pin
Контакт 97 I/O — User I/O pin
Контакт 98 I/O — User I/O pin
Контакт 99 I/O — User I/O pin
Контакт 100 I/O — User I/O pin
Контакт 101 I/O — User I/O pin
Контакт 102 I/O — User I/O pin
Контакт 103 I/O — User I/O pin
Контакт 104 I/O — User I/O pin
Контакт 105 I/O — User I/O pin
Контакт 106 I/O — User I/O pin
Контакт 107 I/O — User I/O pin
Контакт 108 I/O — User I/O pin
Контакт 109 I/O — User I/O pin
Контакт 110 I/O — User I/O pin
Контакт 111 I/O — User I/O pin
Контакт 112 I/O — User I/O pin
Контакт 113 I/O — User I/O pin
Контакт 114 I/O — User I/O pin
Контакт 115 I/O — User I/O pin
Контакт 116 I/O — User I/O pin
Контакт 117 I/O — User I/O pin
Контакт 118 I/O — User I/O pin
Контакт 119 I/O — User I/O pin
Контакт 120 I/O — User I/O pin
Контакт 121 I/O — User I/O pin
Контакт 122 I/O — User I/O pin
Контакт 123 I/O — User I/O pin
Контакт 124 I/O — User I/O pin
Контакт 125 I/O — User I/O pin
Контакт 126 I/O — User I/O pin
Контакт 127 I/O — User I/O pin
Контакт 128 GND — Ground reference
Контакт 129 I/O — User I/O pin
Контакт 130 I/O — User I/O pin
Контакт 131 I/O — User I/O pin
Контакт 132 I/O — User I/O pin
Контакт 133 I/O — User I/O pin
Контакт 134 I/O — User I/O pin
Контакт 135 I/O — User I/O pin
Контакт 136 I/O — User I/O pin
Контакт 137 I/O — User I/O pin
Контакт 138 I/O — User I/O pin
Контакт 139 I/O — User I/O pin
Контакт 140 I/O — User I/O pin
Контакт 141 I/O — User I/O pin
Контакт 142 I/O — User I/O pin
Контакт 143 I/O — User I/O pin
Контакт 144 I/O — User I/O pin
Контакт 145 I/O — User I/O pin
Контакт 146 I/O — User I/O pin
Контакт 147 I/O — User I/O pin
Контакт 148 I/O — User I/O pin
Контакт 149 I/O — User I/O pin
Контакт 150 I/O — User I/O pin
Контакт 151 I/O — User I/O pin
Контакт 152 I/O — User I/O pin
Контакт 153 I/O — User I/O pin
Контакт 154 VCC — +5V core supply
Контакт 155 I/O — User I/O pin
Контакт 156 I/O — User I/O pin
Контакт 157 I/O — User I/O pin
Контакт 158 I/O — User I/O pin
Контакт 159 I/O — User I/O pin
Контакт 160 I/O — User I/O pin
Контакт 161 I/O — User I/O pin
Контакт 162 I/O — User I/O pin
Контакт 163 I/O — User I/O pin
Контакт 164 I/O — User I/O pin
Контакт 165 I/O — User I/O pin
Контакт 166 I/O — User I/O pin
Контакт 167 I/O — User I/O pin
Контакт 168 I/O — User I/O pin
Контакт 169 I/O — User I/O pin
Контакт 170 I/O — User I/O pin
Контакт 171 I/O — User I/O pin
Контакт 172 I/O — User I/O pin
Контакт 173 I/O — User I/O pin
Контакт 174 I/O — User I/O pin
Контакт 175 I/O — User I/O pin
Контакт 176 I/O — User I/O pin
Контакт 177 I/O — User I/O pin
Контакт 178 I/O — User I/O pin
Контакт 179 I/O — User I/O pin
Контакт 180 I/O — User I/O pin
Контакт 181 I/O — User I/O pin
Контакт 182 GND — Ground reference
Контакт 183 I/O — User I/O pin
Контакт 184 I/O — User I/O pin
Контакт 185 I/O — User I/O pin
Контакт 186 I/O — User I/O pin
Контакт 187 I/O — User I/O pin
Контакт 188 I/O — User I/O pin
Контакт 189 I/O — User I/O pin
Контакт 190 I/O — User I/O pin
Контакт 191 I/O — User I/O pin
Контакт 192 I/O — User I/O pin
Контакт 193 I/O — User I/O pin
Контакт 194 I/O — User I/O pin
Контакт 195 I/O — User I/O pin
Контакт 196 I/O — User I/O pin
Контакт 197 I/O — User I/O pin
Контакт 198 I/O — User I/O pin
Контакт 199 I/O — User I/O pin
Контакт 200 I/O — User I/O pin
Контакт 201 I/O — User I/O pin
Контакт 202 I/O — User I/O pin
Контакт 203 I/O — User I/O pin
Контакт 204 I/O — User I/O pin
Контакт 205 I/O — User I/O pin
Контакт 206 I/O — User I/O pin
Контакт 207 I/O — User I/O pin
Контакт 208 I/O — User I/O pin

Типичное применение

EPM9560RZ208-15 подходит для 6 применениеs: Legacy Industrial Control Systems, Telecommunications Backplane Glue Logic, ISA/PCI Bus Address Decoding, Microcontroller Peripheral Expansion, ASIC Prototyping and Logic Consolidation, Legacy Board Repair and Last-Time-Buy Stock.

🏭

Legacy Industrial Control Systems

The EPM9560RZ208-15 fits legacy industrial control systems because its 560 macrocells and 212 user I/Os can replace dozens of discrete 74-series logic devices on a control board, dramatically reducing component count and improving reliability. The device's 15 ns tPD comfortably supports 33 MHz synchronous operation typical of PLC backplanes, motor-control interfaces, and sensor-multiplexing boards. The RQFP-208 package's surface-mount profile also suits modernized control cabinets where vibration resistance is critical. Compared to a discrete logic implementation, a single MAX 9560 reduces PCB area by 60–80% and simplifies BOM management. The device's non-volatile EEPROM configuration means no external boot PROM is required — power-on behavior is deterministic. This makes the EPM9560RZ208-15 a strong candidate for repairing or extending legacy control systems whose original CPLD has failed or whose logic must be updated to support new sensor types.

🌐

Telecommunications Backplane Glue Logic

The EPM9560RZ208-15 fits telecommunications backplane glue-logic applications because its high I/O count (212 pins) can simultaneously address multiple bus segments, control line interfaces, and timing-synchronization signals on a backplane mid-plane. The deterministic tPD = 15 ns timing enables the device to reliably bridge 33 MHz TDM buses, E1/T1 framers, and HDLC controllers without violating setup/hold budgets. The FastTrack continuous interconnect ensures every signal path has the same delay regardless of placement — a critical property for backplane designs where signal-integrity margins are tight. Compared to FPGA alternatives, the MAX 9560's instant-on (no configuration time) and 5V-tolerant I/Os make it simpler to integrate with legacy line-interface units. The RQFP-208 package supports the high pin density required for backplane glue logic. For TDM and SDH backplanes operating at speeds up to 52 Mbps, the EPM9560RZ208-15 is a mature, qualified choice.

🖥️

ISA/PCI Bus Address Decoding

The EPM9560RZ208-15 fits ISA and PCI bus address-decoding applications because its 560 macrocells can decode the full 32-bit address space of a PCI bus while also providing bus-master arbitration, interrupt steering, and wait-state generation in a single device. The 15 ns tPD easily meets the PCI 33 MHz clock-to-output requirements with margin to spare, while the 212 user I/Os comfortably accommodate the PCI bus signals plus several ISA or local-bus peripherals. The non-volatile configuration eliminates the boot-time delay associated with SRAM-based FPGAs — important for systems that must respond to bus arbitration within microseconds of power-up. The deterministic timing model also allows designers to compute worst-case propagation paths without iteration, accelerating board bring-up. Compared to discrete 74F138 / 74F139 decoder trees, a single MAX 9560 reduces part count, lowers propagation skew, and provides a software-configurable decode map that can be revised without PCB changes. This makes the EPM9560RZ208-15 a standard choice for industrial-PCI and CompactPCI single-board computers.

🤖

Microcontroller Peripheral Expansion

The EPM9560RZ208-15 fits microcontroller peripheral-expansion applications because it can synthesize custom peripherals — PWM generators, quadrature decoders, UARTs, and chip-select glue — that extend a host MCU's I/O count and offload timing-critical tasks. The 560 macrocells provide ample capacity for 8–10 synthesized peripherals in a single device, while the 212 user I/Os comfortably handle the multiplexed signal fan-out to sensors, actuators, and external memory. The 5V-tolerant I/Os on most MAX 9000 variants interface directly with 5V MCUs without level shifters, simplifying board design. The non-volatile EEPROM configuration means the peripheral map is available instantly on power-up — important for deterministic motor-control and safety-critical loops. Compared to discrete logic implementations, the MAX 9560 consolidates 10–20 small ICs into one, reducing PCB area by 50–70% and BOM cost. The EPM9560RZ208-15 is widely used in industrial automation, robotics, and embedded control designs where deterministic peripheral behavior is required.

🔬

ASIC Prototyping and Logic Consolidation

The EPM9560RZ208-15 fits ASIC prototyping and logic-consolidation applications because its 12,000 usable gates are sufficient to emulate a small block of a planned gate-array or structured-ASIC design, allowing firmware and system validation to proceed in parallel with ASIC fab. The deterministic timing of the FastTrack interconnect lets designers verify worst-case critical paths against ASIC timing budgets before tape-out, reducing design risk. The 212 user I/Os accommodate the wide busses typical of ASIC datapaths (32–64 bits plus control), and the 5V I/O compatibility simplifies integration with legacy test fixtures. The non-volatile configuration means prototypes can be reprogrammed and reused across multiple ASIC iterations without external PROMs. Compared to FPGA prototyping, the MAX 9560 consumes less power and is less expensive at low volumes, though it has lower density. This makes the EPM9560RZ208-15 a standard choice for prototyping glue logic and peripheral controllers ahead of ASIC migration.

🔧

Legacy Board Repair and Last-Time-Buy Stock

The EPM9560RZ208-15 fits legacy board-repair and last-time-buy stock scenarios because production systems that integrated this part in the late-1990s and 2000s often require functional-equivalent replacements during maintenance cycles. The 560 macrocells, 212 user I/Os, and 15 ns tPD match the exact specifications of the originally-installed part, ensuring that the repaired system performs identically to the original. The RQFP-208 package footprint matches existing PCB land patterns, so no board rework is required. The non-volatile EEPROM configuration ensures the repaired unit behaves identically to the original after programming. Compared to redesigning with a modern CPLD (which would require board respin, requalification, and possibly FCC/CE re-certification), sourcing the same EPM9560RZ208-15 minimizes repair cost and turnaround. This is the primary use case for this part in 2026 — supporting installed-base systems in industrial, telecom, and military/aerospace markets with long service lifetimes.

What is the EPM9560RZ208-15?
The EPM9560RZ208-15 is a member of the Altera MAX 9000 EPLD family, providing 560 macrocells (approximately 12,000 usable gates) in a 208-pin PowerQuad QFP (RQFP) package with a 15 ns pin-to-pin delay. It is built on 0.35 µm CMOS EEPROM technology and supports in-system programming via JTAG. According to the Altera MAX 9000 datasheet, the device targets high-density glue-logic, bus-interface, and state-machine consolidation applications.
How many macrocells and user I/O pins does the EPM9560RZ208-15 have?
The EPM9560RZ208-15 contains 560 macrocells organized into 16 Logic Array Blocks (LABs) and supports up to 212 user I/O pins. According to the Altera MAX 9000 datasheet, this I/O count makes the EPM9560 well suited for parallel bus interfaces, address decoding, and wide datapath applications where multiple discrete 74-series logic devices would otherwise be required.
What is the difference between EPM9560RZ208-15 and EPM9560RC208-15?
Both parts share the same die (560 macrocells, 12,000 usable gates, 15 ns tPD), but differ in package: the EPM9560RZ208-15 uses a 208-pin PowerQuad QFP (RQFP) while the EPM9560RC208-15 uses a 208-pin standard QFP. Pin-out is package-specific, so they are NOT drop-in interchangeable; the R variant is typically used where lower profile or socketed mounting is required.
Is the EPM9560RZ208-15 still in production?
No. The EPM9560RZ208-15 is listed as obsolete by Altera (now Intel) and is no longer in active production. Stock is available only through distributors carrying legacy inventory, brokers, or factory-direct last-time-buy channels. Pricing as of 2026-09-13 reflects scarcity-driven premium rather than volume production cost.
Where can I buy the EPM9560RZ208-15 online?
The EPM9560RZ208-15 can be sourced from legacy-stock distributors, brokers, and the XAIPART product page. Lead time for new orders is typically 4–12 weeks due to obsolete lifecycle status, with prices quoted on a per-unit basis. Pricing as of 2026-09-13 starts at approximately $85 per unit at qty-1.
What is the price of the EPM9560RZ208-15?
The EPM9560RZ208-15 unit price as of 2026-09-13 is approximately $85 at qty-1, with volume discounts down to roughly $55 at qty-1000. Pricing reflects the obsolete lifecycle status and scarcity of remaining stock rather than active-market pricing. Quote-based pricing is recommended for production orders.
What is the lead time for the EPM9560RZ208-15?
Lead time for the EPM9560RZ208-15 ranges from 4 to 12 weeks depending on stock availability at legacy distributors as of 2026-09-13. Because the part is obsolete, brokers and factory-direct last-time-buy channels often provide the only practical path to volume supply. Engineering qualification should be planned for a possible redesign to a current CPLD family.
Where can I download the EPM9560RZ208-15 datasheet PDF?
The EPM9560 datasheet PDF is hosted at alldatasheet.com (182-page mature-device datasheet) and at Altera/Intel's document server. The document covers DC characteristics, AC timing, pinout, and programming specifications for the entire MAX 9000 family, including the EPM9560RZ208-15 variant. Search for 'EPM9560 datasheet' or 'MAX 9000 datasheet' to locate the latest version.
Where can I find the pinout for the EPM9560RZ208-15?
The pinout for the EPM9560RZ208-15 is documented in the MAX 9000 datasheet Section 6 'Package Information'. Pin 1 is identified by the marker dot on the RQFP-208 package. The 208 pins are arranged in a 0.5 mm pitch QFP perimeter layout. Designers should reference the device-specific pinout table, not the family-level diagram, when laying out PCB footprints.
What is a drop-in replacement for the EPM9560RZ208-15?
Drop-in replacements for the EPM9560RZ208-15 within the same MAX 9000 family include the EPM9560RC208-15 (standard QFP, NOT pin-compatible due to package difference), EPM9560RI208-15 (industrial temperature grade), and EPM9560RC208-10 (10 ns faster speed grade). For modern redesign, the Altera MAX II, MAX V, or MAX 10 CPLD families provide functional alternatives with smaller packages but require PCB redesign.
EPM9560RZ208-15 vs EPM9560RC208-15 — which is better for legacy board repair?
For legacy board repair, the choice between EPM9560RZ208-15 and EPM9560RC208-15 depends on the package footprint of the board being repaired. The RZ variant uses a PowerQuad QFP (RQFP-208) while the RC variant uses a standard QFP-208; these packages have different mechanical outlines and pin numbering, so they are not interchangeable. Identify the original package marking on the failed board before ordering a substitute.
When should I choose the EPM9560RZ208-15 over a modern MAX II CPLD?
Choose the EPM9560RZ208-15 only when repairing an existing design that uses the MAX 9000 family footprint, when migrating to a newer CPLD would require a costly board respin, or when sourcing approved-by-contract legacy inventory. For new designs, the Altera MAX II, MAX V, or MAX 10 CPLD families offer lower power, smaller packages (TQFP, BGA), modern I/O standards, and active lifecycle support.
Is the EPM9560RZ208-15 suitable for new industrial control designs?
No. The EPM9560RZ208-15 is obsolete and not recommended for new industrial control designs as of 2026-09-13. Designers should select a current-generation CPLD such as the Altera (Intel) MAX V or MAX 10, which provides smaller packages, lower power, modern I/O standards, and active lifecycle support. The EPM9560RZ208-15 should be reserved for legacy board repair or last-time-buy inventory scenarios.
What is the difference between the Altera MAX 9000 and MAX 7000 CPLD families?
The MAX 9000 family offers higher logic density (up to 560 macrocells / 12,000 usable gates in the EPM9560) compared to the MAX 7000 family (up to 256 macrocells). The MAX 9000 also uses a more advanced interconnect architecture and supports more user I/O pins (up to 212 vs 164). Both families share the 5V core voltage, EEPROM-based in-system programmability, and JTAG programming interface, making them architecturally familiar to MAX 7000 users.

Справочные инженерные данные для EPM9560RZ208-15 — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM9560RZ208-15 when repairing or extending a legacy design that uses the MAX 9000 family in a 208-pin PowerQuad QFP (RQFP-208) package and needs the highest available logic density (560 macrocells, 12,000 usable gates) with a 15 ns pin-to-pin delay. Choose the EPM9560RI208-15 if the same density is needed but the design operates over industrial temperature range (-40C to +85C). Choose the EPM9560RC208-15 only if the board uses a standard QFP-208 footprint rather than the PowerQuad outline. For new designs, migrate to a current-generation CPLD such as the Altera MAX II, MAX V, or MAX 10 family — these offer smaller packages, lower power, modern I/O standards, and active lifecycle support, at the cost of a PCB redesign.

Сравнение с аналогами

Параметр Этот товар EPM9560RI208-15 EPM9560RI208-20 EPM9560RI208-10 EPM9560RC208-15 EPM9480RC208-15 EPM9400RC208-20
Package RQFP-208 (PowerQuad QFP) RQFP-208 - same RQFP-208 - same RQFP-208 - same QFP-208 - different outline QFP-208 - different outline QFP-208 - different outline
Brand Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel)
Macrocells 560 560 560 560 560 480 (-14%) 400 (-29%)
Usable Gates 12,000 12,000 12,000 12,000 12,000 10,000 8,000
Pin-to-Pin Delay (tPD) 15 ns 15 ns (same) 20 ns (slower) 10 ns (faster) 15 ns (same) 15 ns (same) 20 ns (slower)
Family MAX 9000 MAX 9000 MAX 9000 MAX 9000 MAX 9000 MAX 9000 MAX 9000
Lifecycle Status Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete

Ключевые отличия

  • Higher logic density in the same MAX 9000 family (против EPM9480RC208-15)
  • PowerQuad QFP package for low-profile designs (против EPM9560RC208-15)
  • 15 ns speed grade matches the design's synchronous clock budget (против EPM9560RI208-20)

Заметки по проектированию

The RQFP-208 (PowerQuad QFP) package uses a 0.5 mm lead pitch with thermal pad considerations. Recommended PCB land pattern is per IPC-7351 nominal density with 0.6 mm pad width. Place a continuous ground plane on the layer immediately beneath the device to provide a low-impedance return path for the high-pin-count I/O. Decoupling: 0.1 µF ceramic capacitor within 5 mm of each VCC/GND pair, plus a single 10 µF tantalum or polymer bulk capacitor near the device. For mixed 5V/3.3V designs, isolate the MAX 9560 VCCIO bank supply from other 3.3V logic with a ferrite bead to prevent ground bounce coupling through the shared plane.

Estimated: at 33 MHz toggle frequency across 50% of 212 I/Os with 50 pF load, the dynamic power consumption is approximately P = 0.5 × C × V^2 × f × N = 0.5 × 50e-12 × 25 × 33e6 × 106 ≈ 2.2 W. Add quiescent power (~150 mA × 5V = 0.75 W typical) for a total estimated dissipation of ~3 W. The RQFP-208 has a θJA of approximately 25-30 °C/W with 1 oz copper 4-layer board and thermal vias — resulting in a junction temperature rise of ~75-90 °C above ambient at full load. For high-altitude or sealed-enclosure applications, derate toggle activity by 20% or attach a clip-on heatsink to the package top.

Do not assume the EPM9560RZ208-15 is pin-compatible with the EPM9560RC208-15 — the RZ suffix indicates a PowerQuad QFP (RQFP) package with different mechanical outline and pin numbering compared to the standard QFP-208 used by the RC suffix. Verify the original board's package marking before substituting. Also note that MAX 9000 devices require 5V VCC (not 3.3V); connecting 3.3V-only will prevent configuration and may damage the device. JTAG programming requires the four JTAG pins (TDI/TDO/TMS/TCK) to be accessible — ensure they are not assigned to user I/O functions in the Quartus pin assignment file unless pull-ups are provided externally.

Информация о соответствии

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Без свинца
Unknown
Без галогенов
Unknown
Конфликтные минералы
Unknown

Compliance information not present in the verified web data; the EPM9560RZ208-15 is a mature Altera (Intel) part and original-era MAX 9000 devices were typically non-RoHS. Verify with the manufacturer or distributor documentation before using in RoHS-restricted designs.

Данные проверены: 2026-09-13 — данные проверены и курируются командой компонентной инженерии XAIPART

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Связанные компоненты & термины

Altera Intel EPM9560RZ208-15 EPM9560RI208-15 EPM9560RI208-20 EPM9560RI208-10 EPM9560RC208-15 EPM9480RC208-15 EPM9400RC208-20 MAX 9000 EPLD CPLD PLD RQFP-208 PowerQuad QFP JTAG IEEE 1149.1 FastTrack Interconnect macrocell logic array block 5V tolerant I/O in-system programmability industrial control telecommunications backplane PCI bus decoder
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