TPS54120 - Low-Noise 1A Buck + LDO Power Supply | TI
Артикул: TPS54120 ✓ Активен| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $5.2 | $5,20 |
| 10 | $4.68 | $46,80 |
| 100 | $4.16 | $416,00 |
| 500 | $3.75 | $1.875,00 |
| 1.000 | $3.35 | $3.350,00 |
TPS54120 Обзор
An integrated power supply, or PMIC-style power stage, combines multiple regulation stages so a single IC replaces a discrete converter-plus-LDO chain. In the system power hierarchy, the TPS54120 sits within power management ICs (PMICs) -> voltage regulators -> DC-DC converters and LDO linear regulators. By cascading a buck converter with a low-noise LDO, the design attenuates switching ripple before it reaches the load, achieving far lower output noise than a buck regulator alone without the power penalty of an all-linear solution.
Key features include a configurable switching frequency of 200 kHz to 1.2 MHz with frequency synchronization, adjustable soft-start for controlled inrush, power-good output for supply sequencing supervision, adjustable output voltages using external resistor dividers (down to 0.6 V reference per TI documentation conventions), and a fully configurable dc-dc and LDO stage. The high PSR of the integrated LDO stage suppresses buck ripple, making the output suitable for RF, clocking, and precision analog rails.
According to the TI datasheet, typical applications include telecom infrastructure, pico and femto base stations, and powering sensitive clocking distribution where phase noise directly impacts system performance. The single-package integration reduces BOM count and board area versus a discrete two-chip solution.
In design, place the buck switching loop components tightly, and give the LDO stage sufficient headroom so the LDO output stays in regulation; the LDO drop-out determines the minimum buck output setting for a clean final rail.
Аналоги без доработки для TPS54120 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
TPS54120RGYT
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
TPS54120 Максимальные параметры и электрические характеристики
| Функция | Step-down (buck) DC-DC converter + linear (LDO) regulator, dual output |
| Output Current | 1 A |
| Switching Frequency Range | 200 kHz to 1.2 MHz |
| Frequency Synchronization | Yes |
| Плавный пуск | Adjustable |
| Выход Power Good | Yes |
| Защита от сверхтока | Yes |
| UVLO | Fixed |
| Output Discharge | Yes |
| Корпус | VQFN-24 (RGY) 5.5 x 3.5 mm |
| Тип монтажа | Surface Mount |
Конфигурация выводов TPS54120
| Контакт 1 | PVIN — Buck power stage input supply |
| Контакт 3 | EN — Enable input |
| Контакт 5 | SS/TR — Soft-start / tracking adjust |
| Контакт 6 | RT/CLK — Switching frequency set / sync input |
| Контакт 8 | BOOT — High-side gate driver bootstrap |
| Контакт 10 | PH — Buck switch node (inductor connection) |
| Контакт 13 | PGND — Power ground |
| Контакт 15 | VSENSE — Buck feedback voltage sense |
| Контакт 17 | LDOIN — LDO input (from buck output) |
| Контакт 19 | LDOOUT — LDO regulated output |
| Контакт 20 | FB — LDO feedback |
| Контакт 22 | PWRGD — Power good open-drain output |
| Контакт 24 | AGND — Analog ground |
Типичное применение
TPS54120 подходит для 6 применениеs: Telecom Infrastructure Power, Pico and Femto Base Station Clocking Power, Sensitive Clocking Distribution, RF and PLL Power Rails, Precision Analog and Data Converter Supplies, Compact Point-of-Load Modules.
Telecom Infrastructure Power
The TPS54120 fits telecom infrastructure rails that must combine efficiency with low output noise. The integrated buck stage converts the intermediate bus at 200 kHz to 1.2 MHz (synchronizable to a system clock), while the high-PSR LDO stage removes switching ripple before the load. This two-stage integration in a single 24-pin VQFN reduces board area and BOM count versus a discrete converter-plus-LDO chain, and the power-good flag supports rail supervision in multi-supply line cards.
Рекомендуется
Pico and Femto Base Station Clocking Power
Small-cell base stations need compact, clean supplies for PLL and synthesizer circuits. The TPS54120's LDO stage provides high power-supply rejection that suppresses buck ripple, keeping clock phase noise low. The adjustable soft-start controls inrush in power-limited small-cell designs, and frequency synchronization prevents beat frequencies between multiple supplies. Per the TI datasheet, this is a primary named application for the device.
Рекомендуется
Sensitive Clocking Distribution
Jitter attenuators, clock trees, and distribution buffers are highly sensitive to supply noise; even millivolts of ripple can raise phase jitter. The TPS54120 delivers a 1-A low-noise rail by filtering the buck output through its integrated LDO, achieving noise far below a buck-only solution. Using the sync pin locks its switching frequency away from sensitive clock harmonics, and output discharge helps controlled power-down in clock modules.
Рекомендуется
RF and PLL Power Rails
RF synthesizers and PLLs demand supply noise well below typical buck output ripple. The TPS54120's cascaded buck-plus-LDO topology provides high power-supply rejection in one package, so designers avoid a separate LDO IC. Place the device close to the PLL with local output capacitance; the LDO headroom of a few hundred millivolts is sufficient to maintain rejection while keeping dissipation low at 1-A loads.
Рекомендуется
Precision Analog and Data Converter Supplies
High-resolution ADCs and precision amplifiers benefit from low-noise analog supplies. The TPS54120 supplies up to 1 A at ultra-low noise, enough for converter analog rails and reference buffers. The buck stage keeps efficiency high so the final LDO stage dissipates only the headroom delta, and the power-good output allows the system to gate data-converter calibration until supplies are stable.
Рекомендуется
Compact Point-of-Load Modules
Space-constrained boards gain from integrating two regulation stages in one 5.5 x 3.5 mm VQFN-24 package. The TPS54120 replaces a discrete buck plus LDO pair, cutting component count and assembly cost while improving ripple rejection through short internal interconnect. The 200 kHz to 1.2 MHz range allows smaller magnetics at the high-frequency end, supporting dense point-of-load designs in industrial and networking equipment.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для TPS54120 — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | TPS54120RGYT | TPS62912 |
|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Output Current | 1 A | 1 A | 1 A |
| Architecture | Buck + LDO (two-stage, low noise) | Buck + LDO - same | Buck only |
| Frequency Synchronization | Yes | Yes | Yes |
| Spread-Spectrum Clocking | No | No | Yes |
| Power Good Output | Yes | Yes | Yes |
| Integrated LDO Stage | Yes (high PSR) | Yes | No |
Ключевые отличия
- Integrated high-PSR LDO second stage (против TPS62912)
- Two-stage integration saves board area (против Discrete buck + LDO (e.g., TPS54620 + TPS7A4701))
- Wide synchronizable frequency range (против TPS62912)
Заметки по проектированию
Keep the buck hot loop (PVIN input capacitor, BOOT capacitor, PH switch node, PGND) as compact as possible on the top layer; place the inductor within 2-3 mm of the PH pins. Solder the VQFN exposed thermal pad to a grounded copper pour with an array of vias to dissipate heat from both the buck and LDO stages. Follow the TI datasheet layout example for the RGY footprint.
Set the buck output a few hundred millivolts above the desired LDO output so the LDO stays in regulation and maintains power-supply rejection. Too little headroom degrades ripple rejection; too much increases LDO dissipation (P = (V_LDOIN - V_LDOOUT) x I_OUT). At 1 A, budget each extra volt of headroom as 1 W of additional loss in the thermal design.
Use the RT/CLK synchronization feature to lock the switching frequency away from sensitive analog or RF clock harmonics in clocking-distribution systems. Synchronizing multiple TPS54120 instances to a common clock prevents beat-frequency products in multi-rail boards. Slow the frequency toward 200 kHz for higher efficiency, or toward 1.2 MHz for smaller inductors and faster transient response.
Do not omit the soft-start capacitor; without it, inrush current can trip the overcurrent protection during startup into large output capacitance. Route the VSENSE feedback trace away from the PH switch node to avoid noise injection, and use the PWRGD output to hold downstream loads off until the rail is valid.
Информация о соответствии
Compliance data not present in provided verified web data; confirm on TI product page quality/environmental section for TPS54120RGYT/RGYR ordering PN.
