10AX115N3F45E2SG vs 10AX115U3F45E2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115N3F45E2SG sa pamamagitan ng Intel at 10AX115U3F45E2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AX115N3F45E2SG - Arria 10 GX FPGA, 1.15M LEs, 1932-FCBGA | Intel
10AX115N3F45E2SG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115N3F45E2SG | 10AX115U3F45E2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 GX | Arria 10 GX |
| Logic Elements | 1,150,000 | — |
| Embedded Memory | 68,857,856 bits | — |
| User I/Os | 768 | — |
| Packhaging | 1932-ball FCBGA (45 x 45 mm, 1.0 mm pitch) | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Process Technology | 20 nm TSMC | — |
| Speed Grade | -2 (middle) | -2 (E2 commercial/extended) |
| Temperature Grade | E2 (extended) | — |
| Transceivers | Up to 24 channels, 12.5 Gbps GX | — |
| DSP Blocks | Variable-precision, 27 x 27 multipliers | Variable-precision, hardened floating-point |
| Hard Memory Controllers | Yes (DDR3/DDR4/LPDDR3) | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| Hard PCIe IP | PCIe Gen3 x8 (hard IP) | — |
| Hard Processor System | Not included (FPGA-only variant) | — |
| Tindminan RoHS | Compliant | — |
| Uri ng Pagpapasok | Surface Mount (SMT) | — |
| Logic Elements (LE) | — | 1,150,000 |
| Adaptive Logic Modules (ALM) | — | 427,200 |
| Embedded Memory Bits | — | 68,857,856 (≈ 52.99 Mbit) |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Process Node | — | 20 nm Tri-Gate (Intel) |
| Temperature na Operasyon | — | Industrial (junction -40 °C to +100 °C) – device grade U |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| Configuration Method | — | FPGA configuration via serial/parallel flash, JTAG |
| RoHS Compliance | — | Compliant |
| Level ng MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |