5CSEBA2U19C7N vs 5CSEBA2U19C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA2U19C7N sa pamamagitan ng Intel at 5CSEBA2U19C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA2U19C7N - Cyclone V SE SoC FPGA, 25K LE, Dual ARM Cortex-A9 | Intel
5CSEBA2U19C7N ✓ NakahandaIntel
5CSEBA2U19C6N - Cyclone V SE SoC FPGA, 25K LE, ARM Cortex-A9 | Intel
5CSEBA2U19C6N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA2U19C7N | 5CSEBA2U19C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25,000 LE | 25 K |
| Adaptive Logic Modules (ALMs) | 9,430 ALM | — |
| ALUTs | 9,430 | — |
| DSP Blocks | 66 (variable-precision 18x18) | Variable-precision DSP |
| Embedded Memory | 1,400 Kbits (M9K + MLAB) | — |
| HPS Processor | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | 925 MHz |
| L1 Cache (per core) | 32 KB I-cache + 32 KB D-cache | — |
| L2 Cache | 512 KB shared | 512 KB shared |
| User I/O Pins | [DATA_NEEDED: exact user I/O count] | — |
| Packhaging | 484-pin UBGA (19x19 mm, 1.0 mm pitch) | 484-pin UBGA (19x19 mm) |
| Speed Grade | C7 | — |
| Temperature na Operasyon | Commercial / Industrial (TJ from data) | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | Compliant | Compliant |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Operating Temperature Grade | — | Commercial (other) |
| Memory Interfaces | — | DDR2, DDR3, LPDDR2 with ECC |
| HPS Peripherals | — | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC |
| L1 Cache per Core | — | 32 KB I-cache + 32 KB D-cache |
| FPGA-to-HPS Bridges | — | AXI-32/AXI-64, FPGA-to-SDRAM ports |