5CSEBA5U19A7N vs 5CSEBA5U19C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA5U19A7N sa pamamagitan ng Intel at 5CSEBA5U19C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA5U19A7N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19A7N ✓ NakahandaIntel
5CSEBA5U19C7N - Cyclone V SE SoC FPGA 85K LE Dual A9 800MHz | Altera
5CSEBA5U19C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA5U19A7N | 5CSEBA5U19C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 85,000 | 85,000 |
| Process Technology | 28 nm low-power | — |
| Hard Processor System (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 700 MHz | 800 MHz per core |
| Packhaging | 484-pin UBG A (19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Supply Voltage (Core) | 1.1 V | 1.1 V typical |
| Operating Temperature Grade | Automotive (AEC-Q100) -40C to +125C | — |
| I/O Count | 66 (per source listing) | — |
| Memory Interface | DDR3 controller in HPS; external memory interface in FPGA fabric | — |
| DSP Blocks | Variable-precision DSP blocks | Variable-precision, 18x18 / 27x27 multipliers |
| Configuration / Boot Modes | NAND, QSPI, SD/MMC | — |
| Tindminan RoHS | Compliant (per Ampheo listing) | — |
| Automotive Qualification | AEC-Q100 (Automotive grade, indicated by 'A' in part number) | — |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Temperature na Operasyon | — | 0C to +85C (commercial, junction) |
| Speed Grade | — | -7 (standard) |
| Process Node | — | 28 nm low-power (TSMC) |
| Embedded Memory | — | M10K + MLAB blocks, ~4,450 Kbits total |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |