A3PE3000-2FGG896 vs A3PE3000L-FGG896M Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A3PE3000-2FGG896 sa pamamagitan ng Microchip Technology at A3PE3000L-FGG896M sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A3PE3000-2FGG896 - 3M-Gate ProASIC3E Flash FPGA | Microchip
A3PE3000-2FGG896 ✓ NakahandaMicrochip Technology
A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip
A3PE3000L-FGG896M ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A3PE3000-2FGG896 | A3PE3000L-FGG896M |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | ProASIC3E | ProASIC3L (Flash-based FPGA) |
| Number of System Gates | 3,000,000 | — |
| Number of I/Os | 620 | — |
| Supply Voltage (Core) | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Speed Grade | -2 | — |
| Packhaging | 896-BGA / 896-FBGA (31x31 mm, 1.0 mm ball pitch) | 896-ball FBGA (FGG896), 1 mm pitch |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to 85C (TJ) | 0 to 70 C |
| Configuration Memory | On-chip Flash (non-volatile, single chip) | — |
| Technology | CMOS flash | — |
| Soft ARM Support | Optional (per ProASIC3E datasheet) | — |
| Packaging | Tray | — |
| Tindminan RoHS | ROHS3 Compliant (G suffix) | — |
| Manufacturer Lead Time | 8 weeks | — |
| Product Status | Active | — |
| Total System Performance | [DATA_NEEDED: system performance] | — |
| System Gates | — | 3,000,000 |
| Logic Cells | — | 75,264 |
| User I/Os | — | Up to 616 (620 per DigiKey listing) |
| Embedded SRAM | — | 504 kbits true dual-port |
| Process Technology | — | 130-nm, 7-layer metal (6 copper), flash-based CMOS |
| Core Voltage | — | 1.2 V to 1.5 V |
| Volte ng Pagbibigay | — | 1.5 V |
| Logic Family | — | CMOS |
| Configuration | — | Non-volatile flash, live-at-power-up Level 0, single-chip |
| Low-Power Feature | — | Flash*Freeze technology |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Input Features | — | Schmitt trigger option on single-ended inputs; weak pull-up/pull-down |