A42MX16-PQ100 vs A42MX16-PQ100IX39 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A42MX16-PQ100 sa pamamagitan ng Microchip Technology at A42MX16-PQ100IX39 sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A42MX16-PQ100 - 24K Gates 5V FPGA, 100-PQFP | Microchip
A42MX16-PQ100 ✓ NakahandaMicrochip Technology
A42MX16-PQ100IX39 - 24K Gate MX FPGA | Microchip | 100-Pin PQFP
A42MX16-PQ100IX39 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A42MX16-PQ100 | A42MX16-PQ100IX39 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | 42MX (Actel MX) | MX (40MX and 42MX) |
| Logic Gates | 24K gates (up to 54,000 system gates) | — |
| Logic Cells | 608 | 1232 |
| System Frequency | 103 MHz / 172 MHz | — |
| Process Technology | 0.45 um | — |
| Volte ng Pagbibigay | 3.3 V / 5 V | 5.0 V |
| Embedded SRAM | 2.5 kbits configurable dual-port | — |
| Programming Technology | Antifuse (one-time programmable, non-volatile) | — |
| User I/O (PQ100 package) | 83 | — |
| Maximum User I/O (device) | Up to 202 | — |
| Pin Locking | 100% pin locking | — |
| Packhaging | 100-PQFP (BQFP), surface mount | 100-pin PQFP |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Boundary Scan | Yes (JTAG boundary-scan register chain, TDI to TDO) | — |
| Equivalent System Gates | — | 24000 |
| Configurable Logic Blocks (CLBs) | — | 608 |
| User I/O Pins | — | 83 |
| Maksimum na Taktiko ng Oras | — | 56 MHz |
| Hanay ng Temperature na Operasyon | — | -40°C to +85°C (industrial) |
| Terminal Pitch | — | 0.635 mm |
| PCI Compliance | — | PCI Local Bus Specification version 2.1 |
| On-Chip Operation | — | 200 MHz |
| Clock-to-Output | — | 6.1 ns |
| JTAG Boundary Scan | — | IEEE Standard 1149.1 |
| Configuration | — | Antifuse (non-volatile) |