ADC1412D080HN-C18 vs ADC1412D080HN-C1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ADC1412D080HN-C18 sa pamamagitan ng Renesas Electronics at ADC1412D080HN-C1 sa pamamagitan ng Renesas Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Renesas Electronics
ADC1412D080HN-C18 - Dual 14-bit 80MSPS ADC, LVDS DDR | Renesas
ADC1412D080HN-C18 ObsoletePagsanggunian na paghahambing
| Parametro | ADC1412D080HN-C18 | ADC1412D080HN-C1 |
|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Pangangasiwaan | 14 bit | 14 bits |
| Number of Channels | 2 | — |
| Sample Rate (per channel) | 80 Msps | — |
| Architecture | Pipelined | Pipelined |
| Output Interface | CMOS or LVDS DDR (selectable) | — |
| Input Channels | 2 (differential or single-ended) | — |
| Packhaging | 64-VFQFPN (HVQFN) 9x9 mm with exposed pad | 64-VFQFPN / HVQFN-64 (9x9 mm, 0.85 mm height, SOT804-6) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Bilang ng Pin | 64 | 64 |
| Family Sample Rate Options | 65 / 80 / 105 / 125 Msps | — |
| Family Series | ADC1412D SER | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial grade) |
| Volte ng Pagbibigay | [DATA_NEEDED: supply voltage] | — |
| Power Consumption | [DATA_NEEDED: power consumption per channel] | — |
| SNR | [DATA_NEEDED: signal-to-noise ratio] | — |
| SFDR | [DATA_NEEDED: spurious-free dynamic range] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: Moisture Sensitivity Level] |
| Number of Input Channels | — | 2 (dual, simultaneous sampling) |
| Rate ng Pagkupita | — | 80 MSPS |
| Input Type | — | Differential analog inputs |
| Digital Output Interface | — | CMOS or LVDS DDR (selectable) |
| Configuration Interface | — | 3-wire SPI-compatible serial |
| Input Clock | — | Sample-rate dependent, single-ended or differential clock input |
| Supply Voltage (AVDD) | — | 3.3 V (per package datasheet family) |
| Screening Level | — | Industrial |
| Lead-Free Finish | — | [DATA_NEEDED: lead-free / matte tin / NiPdAu] |