CDK1308DILP40 vs CDK1308AILP40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng CDK1308DILP40 sa pamamagitan ng MaxLinear at CDK1308AILP40 sa pamamagitan ng MaxLinear. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | CDK1308DILP40 | CDK1308AILP40 |
|---|---|---|
| Brand | MaxLinear | MaxLinear |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 10 bit | 10 bit |
| Sampling Rate (max) | 80 MSPS | — |
| Number of Channels | 1 | — |
| SNR | 61.6 dB at Fin = 8 MHz | — |
| Power Dissipation | 46 mW | — |
| Analog Supply Voltage | 1.8 V | — |
| Digital I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Output Interface | Parallel CMOS | — |
| Input Type | Single-ended | — |
| Reference | Internal | Internal (no external reference required) |
| Architecture | Pipeline | Proprietary, digital error correction |
| Hanay ng Temperature na Operasyon | -40C to +85C | [DATA_NEEDED: operating temperature range] |
| Packhaging | 40-pin QFN (6x6 mm) | 40-pin QFN |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant (per distributor listings) |
| Pin Compatible With | CDK1307 family | — |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Digital Interface | — | CMOS, parallel |
| Control Interface | — | CMOS |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| Volte ng Pagbibigay | — | [DATA_NEEDED: AVDD / DRVDD values] |
| Manufacturer | — | MaxLinear (formerly Exar Corporation) |