CDK1308DILP40 vs CDK1308AILP40 比較
詳細並排比較 CDK1308DILP40 由 MaxLinear 與 CDK1308AILP40 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | CDK1308DILP40 | CDK1308AILP40 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 解析度 | 10 bit | 10 bit |
| Sampling Rate (max) | 80 MSPS | — |
| Number of Channels | 1 | — |
| SNR | 61.6 dB at Fin = 8 MHz | — |
| Power Dissipation | 46 mW | — |
| Analog Supply Voltage | 1.8 V | — |
| Digital I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Output Interface | Parallel CMOS | — |
| Input Type | Single-ended | — |
| Reference | Internal | Internal (no external reference required) |
| Architecture | Pipeline | Proprietary, digital error correction |
| 工作溫度範圍 | -40C to +85C | [DATA_NEEDED: operating temperature range] |
| 封裝 | 40-pin QFN (6x6 mm) | 40-pin QFN |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant | Compliant (per distributor listings) |
| Pin Compatible With | CDK1307 family | — |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Digital Interface | — | CMOS, parallel |
| Control Interface | — | CMOS |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| 供應電壓 | — | [DATA_NEEDED: AVDD / DRVDD values] |
| Manufacturer | — | MaxLinear (formerly Exar Corporation) |