EP1810GI-45 vs EP1810GM883 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GI-45 sa pamamagitan ng Altera at EP1810GM883 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810GI-45 EP1810GM883
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Type UV Erasable Programmable Logic Device (EPLD) UV-Erasable Programmable Logic Device (EPLD)
Family Altera Classic EPLD Classic EPLD (EP1810 series)
Macrocells 24 48
Flip-Flops 48 —
Propagation Delay (tpd) 45 ns 45 ns (max)
Speed Grade -45 —
Technology CMOS —
Package Type Ceramic Pin Grid Array with UV window —
Bilang ng Pin 68 —
Uri ng Pagpapasok Through-Hole Through-Hole (PGA socket)
Programmable Yes (UV-erasable, electrically programmable) —
Tindminan RoHS Non-compliant (ceramic PGA) [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
Lead-Free No [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -55C to +125C (MIL-STD-883 Class B)
Volte ng Pagbibigay [DATA_NEEDED: VCC range] —
Dedicated Inputs — 12
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Supply Voltage (Vcc) — 4.5 V to 5.5 V (nominal 5 V)
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
Process Technology — CMOS, UV-erasable
Packhaging — 68-Pin Ceramic Pin Grid Array (PGA)
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)

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