EP1810GM883B vs EP1810LC-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GM883B sa pamamagitan ng Altera at EP1810LC-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GM883B | EP1810LC-20T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 5 V |
| Technology | CMOS, UV-erasable | — |
| Temperature na Operasyon | -55 °C to +125 °C (Military, MIL-STD-883B) | 0C to +70C (commercial) |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | PLCC-68 (J-lead) |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| Uri ng Pagpapasok | Through-hole (PGA socket or PCB through-hole) | Surface Mount (socket-compatible) |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Family | — | Altera Classic EPLD |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 900 gates |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |
| Tindminan RoHS | — | Non-compliant (legacy 5V PLCC) |