EP1810GM883B vs EP1810LC-20T 比較
詳細並排比較 EP1810GM883B 由 Altera 與 EP1810LC-20T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GM883B | EP1810LC-20T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 5 V |
| Technology | CMOS, UV-erasable | — |
| 工作溫度 | -55 °C to +125 °C (Military, MIL-STD-883B) | 0C to +70C (commercial) |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | PLCC-68 (J-lead) |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| 安裝類型 | Through-hole (PGA socket or PCB through-hole) | Surface Mount (socket-compatible) |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Family | — | Altera Classic EPLD |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 900 gates |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |
| RoHS 狀態 | — | Non-compliant (legacy 5V PLCC) |