EP1810JC-25 vs EP1810GM883B Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-25 sa pamamagitan ng Intel at EP1810GM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JC-25 EP1810GM883B
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera/Intel Classic EPLD (EP1810 series) —
Macrocells 48 48
Propagation Delay (tPD) 25 ns 50 ns max
Maximum Toggle Frequency [DATA_NEEDED: max fMAX] —
Input Lines 60 (including I/O) —
I/O Lines 48 —
Dedicated Inputs 12 12
External Clock Inputs 4 —
Supply Voltage (VCC) 4.75 V to 5.25 V 4.5 V to 5.5 V
Temperature na Operasyon -40 °C to 85 °C (industrial, per distributor listings) -55 °C to +125 °C (Military, MIL-STD-883B)
Technology CMOS, UV-erasable (windowed ceramic DIP) CMOS, UV-erasable
Packhaging 28-pin ceramic DIP (J) with quartz window —
Uri ng Pagpapasok Through-hole Through-hole (PGA socket or PCB through-hole)
Erasure Method UV light (windowed package) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] —
Katayuan ng Lifecycle NRND (Not Recommended for New Designs) —
Device Family — EP1810 (Classic EPLD)
User Flip-Flops — Up to 64
Total Inputs — 60
I/O Pins — 48 (bidirectional, tri-state)
Package Type — Ceramic Pin Grid Array (PGA), 84 pins
Package Designator — GM (ceramic PGA)
Processing Level — MIL-STD-883B (Class B)
Programming Method — UV-erasable / Altera programming hardware
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Logic Family — TTL-compatible I/O

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