EP1810JC-35 vs EP1810GC-35AB Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-35 sa pamamagitan ng Intel at EP1810GC-35AB sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JC-35 EP1810GC-35AB
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) —
Number of Macrocells 48 48
Propagation Delay (tpd) 35 ns (max) —
Maksimum na Taktiko ng Oras [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) Pin Grid Array (PGA), ceramic
Number of Terminals 68 —
Terminal Form J-Bend —
Hanay ng Temperature na Operasyon 0°C to 70°C (Commercial) —
Temperature Grade Commercial —
Erasure Method UV (quartz-windowed ceramic package) —
Tindminan RoHS Compliant (per Altera listing) unknown
Lead-Free Status Lead-free (per distributor listing) —
Uri ng Pagpapasok Surface Mount (J-Lead) —
Logic Architecture Programmable AND/OR array with macrocell outputs —
Product Family — Classic EPLD
Technology — CMOS EPROM
Number of Usable Gates — 1200
Maximum Inputs — 64
Maximum Outputs — 48
Number of I/O Pins — 48
Dedicated Input Pins — 12
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency — 62.5 MHz
Supply Voltage (VCC) — 5 V
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Programming Method — UV-erasable EPROM, in-system via JTAG-like interface

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