EP1810JC-45 vs EP1810GI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-45 sa pamamagitan ng Altera at EP1810GI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JC-45 | EP1810GI-45 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | Altera Classic EPLD |
| Macrocells | 48 | 24 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns |
| Maksimum na Taktiko ng Oras | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS |
| Maximum Supply Voltage | 5.25 V | — |
| Packhaging | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| Bilang ng Pin | 68 | 68 |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| Uri ng Pagpapasok | Surface Mount | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | Non-compliant (ceramic PGA) |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Flip-Flops | — | 48 |
| Speed Grade | — | -45 |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |