EP1810JC-45 vs EP1810JI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-45 sa pamamagitan ng Altera at EP1810JI-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JC-45 | EP1810JI-35 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 48 |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maksimum na Taktiko ng Oras | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| Packhaging | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Bilang ng Pin | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| Uri ng Pagpapasok | Surface Mount | Through-Hole (J-lead) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Temperature na Operasyon | — | -40C to +85C (Industrial) |
| Volte ng Pagbibigay | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |