EP1810JC-45 vs EP1810JI-35 比較
詳細並排比較 EP1810JC-45 由 Altera 與 EP1810JI-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC-45 | EP1810JI-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 48 |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| 最大時脈頻率 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| 封裝 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 28-pin JLCC (J-leaded ceramic, windowed) |
| 腳位數 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| 安裝類型 | Surface Mount | Through-Hole (J-lead) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| 工作溫度 | — | -40C to +85C (Industrial) |
| 供應電壓 | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |