EP1810JC-45 vs EP1810LC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-45 sa pamamagitan ng Altera at EP1810LC-45 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoletePagsanggunian na paghahambing
| Parametro | EP1810JC-45 | EP1810LC-45 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | Altera Classic EPLD |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns |
| Maksimum na Taktiko ng Oras | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| Packhaging | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 68-pin PLCC (J-lead) |
| Bilang ng Pin | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket compatible) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| Temperature na Operasyon | — | 0 °C to +70 °C (commercial) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |