EP1810JC-45 vs EP1810LC-45 比較
詳細並排比較 EP1810JC-45 由 Altera 與 EP1810LC-45 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete規格比較
| 參數 | EP1810JC-45 | EP1810LC-45 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | Altera Classic EPLD |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns |
| 最大時脈頻率 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| 封裝 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | 68-pin PLCC (J-lead) |
| 腳位數 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| 工作溫度 | — | 0 °C to +70 °C (commercial) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |