EP1810JI-45 vs EP1810JC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-45 sa pamamagitan ng Altera at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JI-45 | EP1810JC-45 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| Technology | CMOS EPROM | CMOS, UV-erasable |
| Package Code | QCCJ | QCCJ |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | Commercial |
| Temperature na Operasyon | -40 °C to +85 °C | — |
| Volte ng Pagbibigay | 5 V (TTL compatible) | — |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Macrocells | — | 48 |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Maksimum na Taktiko ng Oras | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Packhaging | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Bilang ng Pin | — | 68 |
| Uri ng Pagpapasok | — | Surface Mount |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance not stated in verified data] |