EP1810JM-45 vs EP1810JC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JM-45 sa pamamagitan ng Altera at EP1810JC-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JM-45 | EP1810JC-35 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP1810 series) | Classic EPLD (EP1810) |
| Macrocells | 48 | — |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 35 ns (max) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | — |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| Bilang ng Pin | 68 | — |
| Temperature na Operasyon | -55 C to +125 C (military grade) | — |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Uri ng Pagpapasok | Surface Mount (J-lead) | Surface Mount (J-Lead) |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | Compliant (per Altera listing) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| Maksimum na Taktiko ng Oras | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Hanay ng Temperature na Operasyon | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |