EP1810LC-25 vs EP1810LC-20T Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-25 sa pamamagitan ng Altera at EP1810LC-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-25 EP1810LC-20T
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 48
Propagation Delay (tPD) 25 ns —
Dedicated Inputs 12 —
I/O Pins 48 —
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) 5 V
Operating Mode Turbo-only (no slow-power mode) —
Packhaging 68-pin JLCC (J-leaded ceramic chip carrier) —
Package Code LC = 68-pin JLCC —
Uri ng Pagpapasok Surface Mount Surface Mount (socket-compatible)
Technology CMOS EPLD (erasable programmable logic device) —
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow —
Katayuan ng Lifecycle Obsolete (legacy Altera Classic family) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] Non-compliant (legacy 5V PLCC)
Temperature na Operasyon [DATA_NEEDED: temperature grade for LC package] 0C to +70C (commercial)
Family — Altera Classic EPLD
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 900 gates
Logic Array Blocks (LABs) — 4 x 12 macrocells
Maximum Toggle Frequency — 50 MHz
Pin-to-Pin Logic Delay (tPD) — 20 ns
Package Type — PLCC-68 (J-lead)
Configuration Memory — On-chip EEPROM (non-volatile)
Programming Interface — JTAG (IEEE 1149.1) and Altera Master/Slave serial
Shipping Format — Tape & Reel ("T" suffix)

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