EP1810LC-25 vs EP1810LC-20T Karşılaştırma
Ayrıntılı yan yana karşılaştırma EP1810LC-25 tarafından Altera ve EP1810LC-20T tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Özellik Karşılaştırması
| Parametre | EP1810LC-25 | EP1810LC-20T |
|---|---|---|
| Marka | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Obsolete | Obsolete |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | 5 V |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Paket | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Package Code | LC = 68-pin JLCC | — |
| Montaj Türü | Surface Mount | Surface Mount (socket-compatible) |
| Technology | CMOS EPLD (erasable programmable logic device) | — |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Yaşam Döngüsü Durumu | Obsolete (legacy Altera Classic family) | — |
| RoHS Durumu | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | Non-compliant (legacy 5V PLCC) |
| İşletim Sıcaklığı | [DATA_NEEDED: temperature grade for LC package] | 0C to +70C (commercial) |
| Family | — | Altera Classic EPLD |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 900 gates |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Package Type | — | PLCC-68 (J-lead) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |