EP1810LC-30 vs EP1810LC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-30 sa pamamagitan ng Altera at EP1810LC-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-30 | EP1810LC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 48 | 48 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Volte ng Pagbibigay | 5 V (typical) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, low-power (LC) | CMOS EPROM |
| Packhaging | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC |
| Programming | Device programmer or JTAG | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Bilang ng Pins | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| Tindminan RoHS | unknown (legacy ceramic package) | [DATA_NEEDED: rohs status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Maximum Operating Frequency | — | 50 MHz |
| Propagation Delay (tPD) | — | 20 ns |
| Programmability | — | UV-Erasable / OTP |
| Dedicated Inputs | — | 12 |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |
| Uri ng Pagpapasok | — | Surface Mount |