EP1810LC-45 vs EP1810JC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-45 sa pamamagitan ng Rochester Electronics at EP1810JC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-45 EP1810JC-25
Brand Rochester Electronics Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Altera Classic EPLD Altera/Intel Classic EPLD (EP1810 series)
Device Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 900 —
Macro Cells 48 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Logic Array Blocks 4 —
Propagation Delay (tpd) 45 ns —
Maximum Operating Frequency 22.2 MHz —
Supply Voltage (Vcc) 5 V (±5%) —
Process Technology 5 V CMOS EPROM —
Packhaging 68-pin PLCC (J-lead) 28-pin ceramic DIP (J) with quartz window
Temperature na Operasyon 0 °C to +70 °C (commercial) -40 °C to 85 °C (industrial, per distributor listings)
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Through-hole
Tindminan RoHS [DATA_NEEDED: RoHS status of Rochester-sourced part] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free finish] —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Macrocells — 48
Propagation Delay (tPD) — 25 ns
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
Dedicated Inputs — 12
External Clock Inputs — 4
Supply Voltage (VCC) — 4.75 V to 5.25 V
Technology — CMOS, UV-erasable (windowed ceramic DIP)
Erasure Method — UV light (windowed package)
Katayuan ng Lifecycle — NRND (Not Recommended for New Designs)

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