EP1810LI-35 vs EP1810JI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LI-35 sa pamamagitan ng Altera at EP1810JI-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LI-35 | EP1810JI-35 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | 35 (slowest in EP1810L family) | -35 |
| Packhaging | 68-pin PLCC (J-Lead, plastic) | 28-pin JLCC (J-leaded ceramic, windowed) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | — |
| Volte ng Pagbibigay | 5 V (TTL-compatible I/O) | 5 V (typical classic EPLD) |
| Temperature na Operasyon | -40 C to +85 C (industrial, 'I' suffix) | -40C to +85C (Industrial) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Through-Hole (J-lead) |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Programming Interface | — | JEDEC fuse file via legacy programmer |