EP1810LI-35 vs EP1810LI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LI-35 sa pamamagitan ng Altera at EP1810LI-45 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP1810LI-35 | EP1810LI-45 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | 35 (slowest in EP1810L family) | — |
| Packhaging | 68-pin PLCC (J-Lead, plastic) | 68-pin PLCC / PQCC68 (J-Lead) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | CMOS, UV-erasable EPROM configuration |
| Volte ng Pagbibigay | 5 V (TTL-compatible I/O) | 5 V |
| Temperature na Operasyon | -40 C to +85 C (industrial, 'I' suffix) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic |
| Usable Gates | — | 900 |
| Maximum User I/O | — | 64 inputs / 48 outputs |
| Pin-to-Pin Logic Delay (tPD) | — | 45 ns |
| Counter Frequency (fCNT) | — | up to 100 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Hanay ng Temperature na Operasyon | — | -40 C to +85 C (Industrial, 'I' suffix) |
| Logic Blocks | — | 12 LABs of 4 macrocells each |
| Configuration Memory | — | Non-volatile UV-erasable EPROM |
| Programming Method | — | Altera programming hardware with MAX+PLUS II / legacy tools |