EP1M120F484I6M vs EP1M120F484C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1M120F484I6M sa pamamagitan ng Altera at EP1M120F484C8N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1M120F484I6M | EP1M120F484C8N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Mercury (EP1M) | Mercury (EP1M) |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | — |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | FINE LINE BGA-484 |
| Package Code | BGA, 484 balls, Fine-pitch | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | — |
| Speed Grade | -6 (slowest Mercury timing bin) | 8 |
| Volte ng Pagbibigay | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| Tindminan RoHS | Compliant (M revision) | [DATA_NEEDED: RoHS compliance] |
| Logic Family | — | CMOS, SRAM-based |
| Number of Logic Elements | — | 49,152 |
| Embedded Memory | — | 4,800 Kbits (M4K blocks) |
| User I/O Pins | — | 303 |
| Terminal Pitch | — | 1.000 mm |
| Uri ng Pagpapasok | — | Surface Mount |
| Supply Voltage (Core) | — | 1.8 V nominal (1.71 V min, 1.89 V max) |
| Temperature na Operasyon | — | 0 °C to 85 °C (Commercial) |
| Transceivers | — | Up to 8 channels with CDR up to 1.25 Gbps |
| Configuration | — | SRAM, JTAG via Quartus II |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |