EP1S20B672C7N vs EP1S25F672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20B672C7N sa pamamagitan ng Intel at EP1S25F672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20B672C7N | EP1S25F672C7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Stratix | — |
| Family | Stratix (original) | — |
| Process Technology | 0.13 µm CMOS | 0.13 µm CMOS |
| Logic Elements (LEs) | 18,460 | 25,660 |
| LABs / CLBs | 1,846 | — |
| Embedded Memory Bits | 1,669,248 bits | 1,944,576 |
| Maximum User I/O | 426 | 473 |
| Number of Pins / Balls | 672 | — |
| Package Type | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core, VCCINT) | 1.5 V | — |
| Temperature na Operasyon | 0 °C to 85 °C (Commercial Extended) | 0 °C to 85 °C (commercial) |
| Speed Grade | -7 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL rating] |
| Logic Family | CMOS | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm from product page] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | Stratix |
| Logic Array Blocks (LABs) | — | 2,566 |
| Number of I/O Pins | — | 672 (BGA balls) |
| Packhaging | — | 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch |
| Core Supply Voltage (VCCINT) | — | 1.5 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] |
| Configuration Method | — | JTAG / Passive Serial / Active Serial |